Simulation Results: lc_ctrl

 
19/11/2025 16:06:30 sha: 241b623 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 88.27
  • line
  • 97.34
  • cond
  • 79.07
  • toggle
  • 83.11
  • fsm
  • 79.07
  • branch
  • 95.38
  • assert
  • 95.99
  • group
  • 87.95
Validation stages
V1
100.00%
V2
88.75%
V2S
69.64%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
lc_ctrl_smoke 1.730s 78.104us 2 2 100.00
csr_hw_reset 2 2 100.00
lc_ctrl_csr_hw_reset 0.920s 94.070us 2 2 100.00
csr_rw 2 2 100.00
lc_ctrl_csr_rw 0.880s 39.139us 2 2 100.00
csr_bit_bash 2 2 100.00
lc_ctrl_csr_bit_bash 1.220s 104.979us 2 2 100.00
csr_aliasing 2 2 100.00
lc_ctrl_csr_aliasing 1.040s 54.612us 2 2 100.00
csr_mem_rw_with_rand_reset 2 2 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.290s 210.271us 2 2 100.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
lc_ctrl_csr_rw 0.880s 39.139us 2 2 100.00
lc_ctrl_csr_aliasing 1.040s 54.612us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 2 50.00
lc_ctrl_state_post_trans 4.180s 75.633us 1 2 50.00
regwen_during_op 2 2 100.00
lc_ctrl_regwen_during_op 12.550s 752.060us 2 2 100.00
rand_wr_claim_transition_if 2 2 100.00
lc_ctrl_claim_transition_if 0.860s 39.577us 2 2 100.00
lc_prog_failure 2 2 100.00
lc_ctrl_prog_failure 1.700s 115.810us 2 2 100.00
lc_state_failure 0 2 0.00
lc_ctrl_state_failure 3.160s 128.105us 0 2 0.00
lc_errors 2 2 100.00
lc_ctrl_errors 9.760s 636.469us 2 2 100.00
security_escalation 10 14 71.43
lc_ctrl_state_failure 3.160s 128.105us 0 2 0.00
lc_ctrl_prog_failure 1.700s 115.810us 2 2 100.00
lc_ctrl_errors 9.760s 636.469us 2 2 100.00
lc_ctrl_security_escalation 6.920s 1296.794us 2 2 100.00
lc_ctrl_jtag_state_failure 11.200s 5933.115us 0 2 0.00
lc_ctrl_jtag_prog_failure 6.100s 269.757us 2 2 100.00
lc_ctrl_jtag_errors 28.430s 8418.965us 2 2 100.00
jtag_access 26 26 100.00
lc_ctrl_jtag_csr_hw_reset 3.280s 578.474us 2 2 100.00
lc_ctrl_jtag_csr_rw 2.490s 221.006us 2 2 100.00
lc_ctrl_jtag_csr_bit_bash 17.410s 5947.922us 2 2 100.00
lc_ctrl_jtag_csr_aliasing 5.910s 1451.560us 2 2 100.00
lc_ctrl_jtag_same_csr_outstanding 1.290s 22.146us 2 2 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.310s 109.871us 2 2 100.00
lc_ctrl_jtag_alert_test 1.770s 75.718us 2 2 100.00
lc_ctrl_jtag_smoke 3.560s 734.769us 2 2 100.00
lc_ctrl_jtag_state_post_trans 22.600s 7272.245us 2 2 100.00
lc_ctrl_jtag_prog_failure 6.100s 269.757us 2 2 100.00
lc_ctrl_jtag_errors 28.430s 8418.965us 2 2 100.00
lc_ctrl_jtag_access 8.070s 1399.337us 2 2 100.00
lc_ctrl_jtag_regwen_during_op 21.830s 1156.448us 2 2 100.00
jtag_priority 2 2 100.00
lc_ctrl_jtag_priority 2.040s 301.976us 2 2 100.00
lc_ctrl_volatile_unlock 2 2 100.00
lc_ctrl_volatile_unlock_smoke 0.950s 43.046us 2 2 100.00
stress_all 0 2 0.00
lc_ctrl_stress_all 9.240s 899.568us 0 2 0.00
alert_test 2 2 100.00
lc_ctrl_alert_test 1.340s 28.662us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
lc_ctrl_tl_errors 2.060s 42.431us 2 2 100.00
tl_d_illegal_access 2 2 100.00
lc_ctrl_tl_errors 2.060s 42.431us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
lc_ctrl_csr_hw_reset 0.920s 94.070us 2 2 100.00
lc_ctrl_csr_rw 0.880s 39.139us 2 2 100.00
lc_ctrl_csr_aliasing 1.040s 54.612us 2 2 100.00
lc_ctrl_same_csr_outstanding 1.180s 26.977us 2 2 100.00
tl_d_partial_access 8 8 100.00
lc_ctrl_csr_hw_reset 0.920s 94.070us 2 2 100.00
lc_ctrl_csr_rw 0.880s 39.139us 2 2 100.00
lc_ctrl_csr_aliasing 1.040s 54.612us 2 2 100.00
lc_ctrl_same_csr_outstanding 1.180s 26.977us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 4 4 100.00
lc_ctrl_tl_intg_err 3.030s 120.583us 2 2 100.00
lc_ctrl_sec_cm 6.680s 278.309us 2 2 100.00
sec_cm_bus_integrity 2 2 100.00
lc_ctrl_tl_intg_err 3.030s 120.583us 2 2 100.00
sec_cm_transition_config_regwen 2 2 100.00
lc_ctrl_regwen_during_op 12.550s 752.060us 2 2 100.00
sec_cm_manuf_state_sparse 2 4 50.00
lc_ctrl_state_failure 3.160s 128.105us 0 2 0.00
lc_ctrl_sec_cm 6.680s 278.309us 2 2 100.00
sec_cm_transition_ctr_sparse 2 4 50.00
lc_ctrl_state_failure 3.160s 128.105us 0 2 0.00
lc_ctrl_sec_cm 6.680s 278.309us 2 2 100.00
sec_cm_manuf_state_bkgn_chk 2 4 50.00
lc_ctrl_state_failure 3.160s 128.105us 0 2 0.00
lc_ctrl_sec_cm 6.680s 278.309us 2 2 100.00
sec_cm_transition_ctr_bkgn_chk 2 4 50.00
lc_ctrl_state_failure 3.160s 128.105us 0 2 0.00
lc_ctrl_sec_cm 6.680s 278.309us 2 2 100.00
sec_cm_state_config_sparse 2 4 50.00
lc_ctrl_state_failure 3.160s 128.105us 0 2 0.00
lc_ctrl_sec_cm 6.680s 278.309us 2 2 100.00
sec_cm_main_fsm_sparse 2 4 50.00
lc_ctrl_state_failure 3.160s 128.105us 0 2 0.00
lc_ctrl_sec_cm 6.680s 278.309us 2 2 100.00
sec_cm_kmac_fsm_sparse 2 4 50.00
lc_ctrl_state_failure 3.160s 128.105us 0 2 0.00
lc_ctrl_sec_cm 6.680s 278.309us 2 2 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
lc_ctrl_state_failure 3.160s 128.105us 0 2 0.00
lc_ctrl_sec_cm 6.680s 278.309us 2 2 100.00
sec_cm_main_fsm_global_esc 2 2 100.00
lc_ctrl_security_escalation 6.920s 1296.794us 2 2 100.00
sec_cm_main_ctrl_flow_consistency 3 4 75.00
lc_ctrl_state_post_trans 4.180s 75.633us 1 2 50.00
lc_ctrl_jtag_state_post_trans 22.600s 7272.245us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
lc_ctrl_sec_mubi 8.330s 806.305us 2 2 100.00
sec_cm_token_valid_ctrl_mubi 2 2 100.00
lc_ctrl_sec_mubi 8.330s 806.305us 2 2 100.00
sec_cm_token_digest 2 2 100.00
lc_ctrl_sec_token_digest 10.700s 784.279us 2 2 100.00
sec_cm_token_mux_ctrl_redun 2 2 100.00
lc_ctrl_sec_token_mux 5.010s 810.689us 2 2 100.00
sec_cm_token_valid_mux_redun 2 2 100.00
lc_ctrl_sec_token_mux 5.010s 810.689us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 2 0.00
lc_ctrl_stress_all_with_rand_reset 29.700s 2417.006us 0 2 0.00