| V1 |
|
100.00% |
| V2 |
|
93.75% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_smoke | 1 | 1 | 100.00 | |||
| mbx_smoke | 53.000s | 75160.566us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 29.524us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| mbx_csr_rw | 2.000s | 13.932us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| mbx_csr_bit_bash | 2.000s | 166.719us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| mbx_csr_aliasing | 1.000s | 21.539us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| mbx_csr_mem_rw_with_rand_reset | 2.000s | 25.447us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| mbx_csr_rw | 2.000s | 13.932us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 21.539us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_stress | 1 | 1 | 100.00 | |||
| mbx_stress | 79.000s | 38077.921us | 1 | 1 | 100.00 | |
| mbx_max_activity | 1 | 1 | 100.00 | |||
| mbx_stress_zero_delays | 67.000s | 10710.363us | 1 | 1 | 100.00 | |
| mbx_imbx_oob | 0 | 1 | 0.00 | |||
| mbx_imbx_oob | 9.000s | 1263.777us | 0 | 1 | 0.00 | |
| mbx_doe_intr_msg | 1 | 1 | 100.00 | |||
| mbx_doe_intr_msg | 18.000s | 4117.420us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| mbx_alert_test | 2.000s | 14.248us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| mbx_intr_test | 2.000s | 17.808us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 2.000s | 65.260us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 2.000s | 65.260us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 29.524us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 2.000s | 13.932us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 21.539us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 30.106us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 29.524us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 2.000s | 13.932us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 21.539us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 30.106us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| mbx_sec_cm | 2.000s | 37.045us | 1 | 1 | 100.00 | |
| mbx_tl_intg_err | 2.000s | 261.644us | 1 | 1 | 100.00 | |