Simulation Results: rom_ctrl

 
19/11/2025 16:06:30 sha: 241b623 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 97.79
  • line
  • 99.46
  • cond
  • 95.25
  • toggle
  • 99.01
  • fsm
  • 100.0
  • branch
  • 98.91
  • assert
  • 95.49
  • group
  • 96.42
Validation stages
V1
100.00%
V2
100.00%
V2S
54.17%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 10.240s 4185.548us 2 2 100.00
csr_hw_reset 2 2 100.00
rom_ctrl_csr_hw_reset 10.260s 605.539us 2 2 100.00
csr_rw 2 2 100.00
rom_ctrl_csr_rw 7.800s 1939.950us 2 2 100.00
csr_bit_bash 2 2 100.00
rom_ctrl_csr_bit_bash 7.420s 810.382us 2 2 100.00
csr_aliasing 2 2 100.00
rom_ctrl_csr_aliasing 6.970s 2775.573us 2 2 100.00
csr_mem_rw_with_rand_reset 2 2 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.060s 1495.240us 2 2 100.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
rom_ctrl_csr_rw 7.800s 1939.950us 2 2 100.00
rom_ctrl_csr_aliasing 6.970s 2775.573us 2 2 100.00
mem_walk 2 2 100.00
rom_ctrl_mem_walk 8.940s 6587.727us 2 2 100.00
mem_partial_access 2 2 100.00
rom_ctrl_mem_partial_access 5.660s 463.654us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 8.470s 310.465us 2 2 100.00
stress_all 2 2 100.00
rom_ctrl_stress_all 21.470s 3275.175us 2 2 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 13.630s 399.965us 2 2 100.00
alert_test 2 2 100.00
rom_ctrl_alert_test 8.260s 209.139us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
rom_ctrl_tl_errors 9.180s 206.761us 2 2 100.00
tl_d_illegal_access 2 2 100.00
rom_ctrl_tl_errors 9.180s 206.761us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
rom_ctrl_csr_hw_reset 10.260s 605.539us 2 2 100.00
rom_ctrl_csr_rw 7.800s 1939.950us 2 2 100.00
rom_ctrl_csr_aliasing 6.970s 2775.573us 2 2 100.00
rom_ctrl_same_csr_outstanding 7.530s 291.264us 2 2 100.00
tl_d_partial_access 8 8 100.00
rom_ctrl_csr_hw_reset 10.260s 605.539us 2 2 100.00
rom_ctrl_csr_rw 7.800s 1939.950us 2 2 100.00
rom_ctrl_csr_aliasing 6.970s 2775.573us 2 2 100.00
rom_ctrl_same_csr_outstanding 7.530s 291.264us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 121.220s 7473.595us 1 2 50.00
passthru_mem_tl_intg_err 2 2 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.480s 2054.471us 2 2 100.00
tl_intg_err 2 4 50.00
rom_ctrl_sec_cm 236.230s 463.871us 0 2 0.00
rom_ctrl_tl_intg_err 55.570s 1181.418us 2 2 100.00
prim_fsm_check 0 2 0.00
rom_ctrl_sec_cm 236.230s 463.871us 0 2 0.00
prim_count_check 0 2 0.00
rom_ctrl_sec_cm 236.230s 463.871us 0 2 0.00
sec_cm_checker_ctr_consistency 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 121.220s 7473.595us 1 2 50.00
sec_cm_checker_ctrl_flow_consistency 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 121.220s 7473.595us 1 2 50.00
sec_cm_checker_fsm_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 121.220s 7473.595us 1 2 50.00
sec_cm_compare_ctrl_flow_consistency 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 121.220s 7473.595us 1 2 50.00
sec_cm_compare_ctr_consistency 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 121.220s 7473.595us 1 2 50.00
sec_cm_compare_ctr_redun 0 2 0.00
rom_ctrl_sec_cm 236.230s 463.871us 0 2 0.00
sec_cm_fsm_sparse 0 2 0.00
rom_ctrl_sec_cm 236.230s 463.871us 0 2 0.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 10.240s 4185.548us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 10.240s 4185.548us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 10.240s 4185.548us 2 2 100.00
sec_cm_bus_integrity 2 2 100.00
rom_ctrl_tl_intg_err 55.570s 1181.418us 2 2 100.00
sec_cm_bus_local_esc 3 4 75.00
rom_ctrl_corrupt_sig_fatal_chk 121.220s 7473.595us 1 2 50.00
rom_ctrl_kmac_err_chk 13.630s 399.965us 2 2 100.00
sec_cm_mux_mubi 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 121.220s 7473.595us 1 2 50.00
sec_cm_mux_consistency 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 121.220s 7473.595us 1 2 50.00
sec_cm_ctrl_redun 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 121.220s 7473.595us 1 2 50.00
sec_cm_ctrl_mem_integrity 2 2 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.480s 2054.471us 2 2 100.00
sec_cm_tlul_fifo_ctr_redun 0 2 0.00
rom_ctrl_sec_cm 236.230s 463.871us 0 2 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 2 100.00
rom_ctrl_stress_all_with_rand_reset 228.540s 2743.879us 2 2 100.00