| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| rstmgr_smoke | 1.260s | 75.093us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.060s | 64.444us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rstmgr_csr_rw | 0.860s | 36.943us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rstmgr_csr_bit_bash | 1.720s | 51.780us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rstmgr_csr_aliasing | 1.290s | 50.489us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| rstmgr_csr_mem_rw_with_rand_reset | 0.970s | 66.489us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rstmgr_csr_rw | 0.860s | 36.943us | 1 | 1 | 100.00 | |
| rstmgr_csr_aliasing | 1.290s | 50.489us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_stretcher | 1 | 1 | 100.00 | |||
| rstmgr_por_stretcher | 1.120s | 115.281us | 1 | 1 | 100.00 | |
| sw_rst | 1 | 1 | 100.00 | |||
| rstmgr_sw_rst | 1.070s | 36.564us | 1 | 1 | 100.00 | |
| sw_rst_reset_race | 1 | 1 | 100.00 | |||
| rstmgr_sw_rst_reset_race | 1.150s | 69.477us | 1 | 1 | 100.00 | |
| reset_info | 1 | 1 | 100.00 | |||
| rstmgr_reset | 5.760s | 820.280us | 1 | 1 | 100.00 | |
| cpu_info | 1 | 1 | 100.00 | |||
| rstmgr_reset | 5.760s | 820.280us | 1 | 1 | 100.00 | |
| alert_info | 1 | 1 | 100.00 | |||
| rstmgr_reset | 5.760s | 820.280us | 1 | 1 | 100.00 | |
| reset_info_capture | 1 | 1 | 100.00 | |||
| rstmgr_reset | 5.760s | 820.280us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| rstmgr_stress_all | 17.880s | 2567.472us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rstmgr_alert_test | 1.190s | 36.429us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| rstmgr_tl_errors | 2.110s | 70.273us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| rstmgr_tl_errors | 2.110s | 70.273us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.060s | 64.444us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 0.860s | 36.943us | 1 | 1 | 100.00 | |
| rstmgr_csr_aliasing | 1.290s | 50.489us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 1.110s | 70.980us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.060s | 64.444us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 0.860s | 36.943us | 1 | 1 | 100.00 | |
| rstmgr_csr_aliasing | 1.290s | 50.489us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 1.110s | 70.980us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| rstmgr_sec_cm | 16.310s | 3425.748us | 1 | 1 | 100.00 | |
| rstmgr_tl_intg_err | 3.990s | 642.521us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| rstmgr_sec_cm | 16.310s | 3425.748us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| rstmgr_sec_cm | 16.310s | 3425.748us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rstmgr_tl_intg_err | 3.990s | 642.521us | 1 | 1 | 100.00 | |
| sec_cm_scan_intersig_mubi | 1 | 1 | 100.00 | |||
| rstmgr_sec_cm_scan_intersig_mubi | 1.110s | 63.814us | 1 | 1 | 100.00 | |
| sec_cm_leaf_rst_bkgn_chk | 1 | 1 | 100.00 | |||
| rstmgr_leaf_rst_cnsty | 3.810s | 467.203us | 1 | 1 | 100.00 | |
| sec_cm_leaf_rst_shadow | 1 | 1 | 100.00 | |||
| rstmgr_leaf_rst_shadow_attack | 2.170s | 292.997us | 1 | 1 | 100.00 | |
| sec_cm_leaf_fsm_sparse | 1 | 1 | 100.00 | |||
| rstmgr_sec_cm | 16.310s | 3425.748us | 1 | 1 | 100.00 | |
| sec_cm_sw_rst_config_regwen | 1 | 1 | 100.00 | |||
| rstmgr_csr_rw | 0.860s | 36.943us | 1 | 1 | 100.00 | |
| sec_cm_dump_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| rstmgr_csr_rw | 0.860s | 36.943us | 1 | 1 | 100.00 | |