| V1 |
|
93.55% |
| V2 |
|
64.29% |
| V2S |
|
100.00% |
| V3 |
|
0.00% |
| unmapped |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| rv_dm_smoke | 1.900s | 1645.379us | 1 | 1 | 100.00 | |
| jtag_dtm_csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_hw_reset | 2.480s | 819.550us | 1 | 1 | 100.00 | |
| jtag_dtm_csr_rw | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_rw | 1.040s | 409.063us | 1 | 1 | 100.00 | |
| jtag_dtm_csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_bit_bash | 9.120s | 16035.069us | 1 | 1 | 100.00 | |
| jtag_dtm_csr_aliasing | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_aliasing | 1.200s | 365.499us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_hw_reset | 4.380s | 18416.363us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_rw | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_rw | 6.040s | 5067.286us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_bit_bash | 98.020s | 51695.761us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_aliasing | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_aliasing | 35.420s | 59907.543us | 1 | 1 | 100.00 | |
| jtag_dmi_cmderr_busy | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_busy | 1.160s | 312.541us | 1 | 1 | 100.00 | |
| jtag_dmi_cmderr_not_supported | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_not_supported | 1.390s | 392.894us | 1 | 1 | 100.00 | |
| cmderr_exception | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_exception | 0.740s | 208.656us | 1 | 1 | 100.00 | |
| mem_tl_access_resuming | 0 | 1 | 0.00 | |||
| rv_dm_mem_tl_access_resuming | 0.830s | 76.023us | 0 | 1 | 0.00 | |
| mem_tl_access_halted | 1 | 1 | 100.00 | |||
| rv_dm_mem_tl_access_halted | 1.780s | 626.638us | 1 | 1 | 100.00 | |
| cmderr_halt_resume | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_halt_resume | 1.620s | 438.511us | 1 | 1 | 100.00 | |
| dataaddr_rw_access | 1 | 1 | 100.00 | |||
| rv_dm_dataaddr_rw_access | 0.670s | 101.734us | 1 | 1 | 100.00 | |
| halt_resume | 1 | 1 | 100.00 | |||
| rv_dm_halt_resume_whereto | 1.360s | 364.176us | 1 | 1 | 100.00 | |
| progbuf_busy | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_busy | 1.160s | 312.541us | 1 | 1 | 100.00 | |
| abstractcmd_status | 1 | 1 | 100.00 | |||
| rv_dm_abstractcmd_status | 1.130s | 532.623us | 1 | 1 | 100.00 | |
| progbuf_read_write_execute | 1 | 1 | 100.00 | |||
| rv_dm_progbuf_read_write_execute | 1.300s | 654.512us | 1 | 1 | 100.00 | |
| progbuf_exception | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_exception | 0.740s | 208.656us | 1 | 1 | 100.00 | |
| rom_read_access | 1 | 1 | 100.00 | |||
| rv_dm_rom_read_access | 0.750s | 61.150us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_dm_csr_hw_reset | 1.330s | 113.192us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rv_dm_csr_rw | 2.000s | 142.853us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_dm_csr_bit_bash | 19.780s | 742.761us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_dm_csr_aliasing | 51.570s | 5177.265us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_dm_csr_mem_rw_with_rand_reset | 0.810s | 65.223us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rv_dm_csr_aliasing | 51.570s | 5177.265us | 1 | 1 | 100.00 | |
| rv_dm_csr_rw | 2.000s | 142.853us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| rv_dm_mem_walk | 0.830s | 53.139us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| rv_dm_mem_partial_access | 0.660s | 39.142us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| idcode | 1 | 1 | 100.00 | |||
| rv_dm_smoke | 1.900s | 1645.379us | 1 | 1 | 100.00 | |
| jtag_dtm_hard_reset | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_hard_reset | 0.830s | 268.287us | 1 | 1 | 100.00 | |
| jtag_dtm_idle_hint | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_idle_hint | 0.850s | 146.149us | 1 | 1 | 100.00 | |
| jtag_dmi_failed_op | 1 | 1 | 100.00 | |||
| rv_dm_dmi_failed_op | 0.790s | 295.561us | 1 | 1 | 100.00 | |
| jtag_dmi_dm_inactive | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_dm_inactive | 0.900s | 576.507us | 1 | 1 | 100.00 | |
| sba | 0 | 2 | 0.00 | |||
| rv_dm_sba_tl_access | 351.080s | 300000.000us | 0 | 1 | 0.00 | |
| rv_dm_delayed_resp_sba_tl_access | 309.610s | 300000.000us | 0 | 1 | 0.00 | |
| bad_sba | 0 | 1 | 0.00 | |||
| rv_dm_bad_sba_tl_access | 657.420s | 300000.000us | 0 | 1 | 0.00 | |
| sba_autoincrement | 0 | 1 | 0.00 | |||
| rv_dm_autoincr_sba_tl_access | 268.410s | 300000.000us | 0 | 1 | 0.00 | |
| jtag_dmi_debug_disabled | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dmi_debug_disabled | 0.990s | 421.772us | 0 | 1 | 0.00 | |
| sba_debug_disabled | 1 | 1 | 100.00 | |||
| rv_dm_sba_debug_disabled | 6.310s | 3244.566us | 1 | 1 | 100.00 | |
| ndmreset_req | 1 | 1 | 100.00 | |||
| rv_dm_ndmreset_req | 1.240s | 190.847us | 1 | 1 | 100.00 | |
| hart_unavail | 0 | 1 | 0.00 | |||
| rv_dm_hart_unavail | 0.840s | 59.639us | 0 | 1 | 0.00 | |
| tap_ctrl_transitions | 1 | 2 | 50.00 | |||
| rv_dm_tap_fsm | 3.770s | 7031.207us | 1 | 1 | 100.00 | |
| rv_dm_tap_fsm_rand_reset | 0.900s | 28.708us | 0 | 1 | 0.00 | |
| hartsel_warl | 1 | 1 | 100.00 | |||
| rv_dm_hartsel_warl | 1.350s | 367.260us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| rv_dm_stress_all | 7053.610s | 10000000.000us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rv_dm_alert_test | 0.770s | 79.233us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| rv_dm_tl_errors | 1.090s | 24.320us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| rv_dm_tl_errors | 1.090s | 24.320us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| rv_dm_csr_aliasing | 51.570s | 5177.265us | 1 | 1 | 100.00 | |
| rv_dm_csr_hw_reset | 1.330s | 113.192us | 1 | 1 | 100.00 | |
| rv_dm_csr_rw | 2.000s | 142.853us | 1 | 1 | 100.00 | |
| rv_dm_same_csr_outstanding | 3.150s | 119.456us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| rv_dm_csr_aliasing | 51.570s | 5177.265us | 1 | 1 | 100.00 | |
| rv_dm_csr_hw_reset | 1.330s | 113.192us | 1 | 1 | 100.00 | |
| rv_dm_csr_rw | 2.000s | 142.853us | 1 | 1 | 100.00 | |
| rv_dm_same_csr_outstanding | 3.150s | 119.456us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| rv_dm_sec_cm | 1.700s | 802.014us | 1 | 1 | 100.00 | |
| rv_dm_tl_intg_err | 28.940s | 5903.059us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rv_dm_tl_intg_err | 28.940s | 5903.059us | 1 | 1 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 2 | 2 | 100.00 | |||
| rv_dm_sba_debug_disabled | 6.310s | 3244.566us | 1 | 1 | 100.00 | |
| rv_dm_debug_disabled | 0.850s | 140.600us | 1 | 1 | 100.00 | |
| sec_cm_lc_dft_en_intersig_mubi | 2 | 2 | 100.00 | |||
| rv_dm_sba_debug_disabled | 6.310s | 3244.566us | 1 | 1 | 100.00 | |
| rv_dm_debug_disabled | 0.850s | 140.600us | 1 | 1 | 100.00 | |
| sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 1 | 1 | 100.00 | |||
| rv_dm_smoke | 1.900s | 1645.379us | 1 | 1 | 100.00 | |
| sec_cm_dm_en_ctrl_lc_gated | 1 | 1 | 100.00 | |||
| rv_dm_buffered_enable | 0.850s | 106.122us | 1 | 1 | 100.00 | |
| sec_cm_sba_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| rv_dm_sparse_lc_gate_fsm | 0.890s | 86.918us | 1 | 1 | 100.00 | |
| sec_cm_mem_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| rv_dm_sparse_lc_gate_fsm | 0.890s | 86.918us | 1 | 1 | 100.00 | |
| sec_cm_exec_ctrl_mubi | 1 | 1 | 100.00 | |||
| rv_dm_buffered_enable | 0.850s | 106.122us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_dm_stress_all_with_rand_reset | 0.740s | 56.778us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 0 | 1 | 0.00 | |||
| rv_dm_scanmode | 153.000s | 300000.000us | 0 | 1 | 0.00 | |