Simulation Results: spi_device

 
19/11/2025 16:06:30 sha: 241b623 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 87.86
  • line
  • 99.01
  • cond
  • 95.51
  • toggle
  • 83.36
  • fsm
  • 89.36
  • branch
  • 98.18
  • assert
  • 94.16
  • group
  • 55.46
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 50.640s 20655.512us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.460s 524.974us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.100s 133.645us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 18.570s 1218.257us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 10.150s 877.246us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.910s 54.565us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.100s 133.645us 1 1 100.00
spi_device_csr_aliasing 10.150s 877.246us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.720s 37.443us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.720s 47.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.810s 19.584us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.750s 1.739us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.730s 11.499us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.370s 209.238us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.370s 209.238us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 6.030s 4718.845us 1 1 100.00
spi_device_tpm_sts_read 0.980s 66.663us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 2.750s 1974.795us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 6.240s 4846.751us 1 1 100.00
spi_device_flash_all 0.950s 34.574us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.280s 392.365us 1 1 100.00
spi_device_flash_all 0.950s 34.574us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.280s 392.365us 1 1 100.00
spi_device_flash_all 0.950s 34.574us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 0.950s 34.574us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 11.110s 2266.253us 1 1 100.00
spi_device_flash_all 0.950s 34.574us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 11.110s 2266.253us 1 1 100.00
spi_device_flash_all 0.950s 34.574us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 11.110s 2266.253us 1 1 100.00
spi_device_flash_all 0.950s 34.574us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 11.110s 2266.253us 1 1 100.00
spi_device_flash_all 0.950s 34.574us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 11.110s 2266.253us 1 1 100.00
spi_device_flash_all 0.950s 34.574us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.250s 334.779us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 11.960s 3064.934us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 11.960s 3064.934us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 11.960s 3064.934us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.400s 58.473us 1 1 100.00
spi_device_read_buffer_direct 2.470s 245.450us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 11.960s 3064.934us 1 1 100.00
spi_device_flash_all 0.950s 34.574us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 0.950s 34.574us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 0.950s 34.574us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 5.440s 432.843us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 5.440s 432.843us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 50.640s 20655.512us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 23.300s 7522.545us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 41.590s 7069.417us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.830s 11.694us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.800s 43.402us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.470s 189.295us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.470s 189.295us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.460s 524.974us 1 1 100.00
spi_device_csr_rw 1.100s 133.645us 1 1 100.00
spi_device_csr_aliasing 10.150s 877.246us 1 1 100.00
spi_device_same_csr_outstanding 2.440s 39.756us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.460s 524.974us 1 1 100.00
spi_device_csr_rw 1.100s 133.645us 1 1 100.00
spi_device_csr_aliasing 10.150s 877.246us 1 1 100.00
spi_device_same_csr_outstanding 2.440s 39.756us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.200s 221.475us 1 1 100.00
spi_device_tl_intg_err 5.940s 375.283us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.940s 375.283us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 18.950s 2255.243us 1 1 100.00