Simulation Results: sram_ctrl

 
19/11/2025 16:06:30 sha: 241b623 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 94.41
  • line
  • 98.61
  • cond
  • 92.29
  • toggle
  • 90.66
  • fsm
  • 90.48
  • branch
  • 96.72
  • assert
  • 95.65
  • group
  • 96.47
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
sram_ctrl_smoke 4.690s 2653.740us 2 2 100.00
csr_hw_reset 2 2 100.00
sram_ctrl_csr_hw_reset 0.730s 94.488us 2 2 100.00
csr_rw 2 2 100.00
sram_ctrl_csr_rw 0.720s 60.476us 2 2 100.00
csr_bit_bash 2 2 100.00
sram_ctrl_csr_bit_bash 1.510s 80.414us 2 2 100.00
csr_aliasing 2 2 100.00
sram_ctrl_csr_aliasing 0.790s 15.234us 2 2 100.00
csr_mem_rw_with_rand_reset 2 2 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.780s 1578.288us 2 2 100.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
sram_ctrl_csr_rw 0.720s 60.476us 2 2 100.00
sram_ctrl_csr_aliasing 0.790s 15.234us 2 2 100.00
mem_walk 2 2 100.00
sram_ctrl_mem_walk 259.890s 82782.727us 2 2 100.00
mem_partial_access 2 2 100.00
sram_ctrl_mem_partial_access 122.390s 31361.846us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 2 2 100.00
sram_ctrl_multiple_keys 584.730s 15137.352us 2 2 100.00
stress_pipeline 2 2 100.00
sram_ctrl_stress_pipeline 179.320s 4213.206us 2 2 100.00
bijection 2 2 100.00
sram_ctrl_bijection 934.530s 19472.885us 2 2 100.00
access_during_key_req 2 2 100.00
sram_ctrl_access_during_key_req 603.990s 15188.567us 2 2 100.00
lc_escalation 2 2 100.00
sram_ctrl_lc_escalation 27.300s 33326.045us 2 2 100.00
executable 2 2 100.00
sram_ctrl_executable 364.680s 9776.509us 2 2 100.00
partial_access 4 4 100.00
sram_ctrl_partial_access 47.110s 2644.830us 2 2 100.00
sram_ctrl_partial_access_b2b 185.630s 9426.228us 2 2 100.00
max_throughput 6 6 100.00
sram_ctrl_max_throughput 29.540s 1515.461us 2 2 100.00
sram_ctrl_throughput_w_partial_write 13.380s 14440.357us 2 2 100.00
sram_ctrl_throughput_w_readback 16.800s 3336.829us 2 2 100.00
regwen 2 2 100.00
sram_ctrl_regwen 514.940s 58672.641us 2 2 100.00
ram_cfg 2 2 100.00
sram_ctrl_ram_cfg 2.100s 1980.607us 2 2 100.00
stress_all 2 2 100.00
sram_ctrl_stress_all 3046.070s 498501.654us 2 2 100.00
alert_test 2 2 100.00
sram_ctrl_alert_test 0.800s 15.080us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
sram_ctrl_tl_errors 3.100s 150.933us 2 2 100.00
tl_d_illegal_access 2 2 100.00
sram_ctrl_tl_errors 3.100s 150.933us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
sram_ctrl_csr_hw_reset 0.730s 94.488us 2 2 100.00
sram_ctrl_csr_rw 0.720s 60.476us 2 2 100.00
sram_ctrl_csr_aliasing 0.790s 15.234us 2 2 100.00
sram_ctrl_same_csr_outstanding 0.710s 40.555us 2 2 100.00
tl_d_partial_access 8 8 100.00
sram_ctrl_csr_hw_reset 0.730s 94.488us 2 2 100.00
sram_ctrl_csr_rw 0.720s 60.476us 2 2 100.00
sram_ctrl_csr_aliasing 0.790s 15.234us 2 2 100.00
sram_ctrl_same_csr_outstanding 0.710s 40.555us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 2 2 100.00
sram_ctrl_passthru_mem_tl_intg_err 16.180s 10881.658us 2 2 100.00
tl_intg_err 2 4 50.00
sram_ctrl_sec_cm 0.750s 2.561us 0 2 0.00
sram_ctrl_tl_intg_err 1.900s 367.888us 2 2 100.00
prim_count_check 0 2 0.00
sram_ctrl_sec_cm 0.750s 2.561us 0 2 0.00
sec_cm_bus_integrity 2 2 100.00
sram_ctrl_tl_intg_err 1.900s 367.888us 2 2 100.00
sec_cm_ctrl_config_regwen 2 2 100.00
sram_ctrl_regwen 514.940s 58672.641us 2 2 100.00
sec_cm_readback_config_regwen 2 2 100.00
sram_ctrl_regwen 514.940s 58672.641us 2 2 100.00
sec_cm_exec_config_regwen 2 2 100.00
sram_ctrl_csr_rw 0.720s 60.476us 2 2 100.00
sec_cm_exec_config_mubi 2 2 100.00
sram_ctrl_executable 364.680s 9776.509us 2 2 100.00
sec_cm_exec_intersig_mubi 2 2 100.00
sram_ctrl_executable 364.680s 9776.509us 2 2 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
sram_ctrl_executable 364.680s 9776.509us 2 2 100.00
sec_cm_lc_escalate_en_intersig_mubi 2 2 100.00
sram_ctrl_lc_escalation 27.300s 33326.045us 2 2 100.00
sec_cm_prim_ram_ctrl_mubi 2 2 100.00
sram_ctrl_mubi_enc_err 3.670s 676.120us 2 2 100.00
sec_cm_mem_integrity 2 2 100.00
sram_ctrl_passthru_mem_tl_intg_err 16.180s 10881.658us 2 2 100.00
sec_cm_mem_readback 2 2 100.00
sram_ctrl_readback_err 3.800s 2655.021us 2 2 100.00
sec_cm_mem_scramble 2 2 100.00
sram_ctrl_smoke 4.690s 2653.740us 2 2 100.00
sec_cm_addr_scramble 2 2 100.00
sram_ctrl_smoke 4.690s 2653.740us 2 2 100.00
sec_cm_instr_bus_lc_gated 2 2 100.00
sram_ctrl_executable 364.680s 9776.509us 2 2 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 2 0.00
sram_ctrl_sec_cm 0.750s 2.561us 0 2 0.00
sec_cm_key_global_esc 2 2 100.00
sram_ctrl_lc_escalation 27.300s 33326.045us 2 2 100.00
sec_cm_key_local_esc 0 2 0.00
sram_ctrl_sec_cm 0.750s 2.561us 0 2 0.00
sec_cm_init_ctr_redun 0 2 0.00
sram_ctrl_sec_cm 0.750s 2.561us 0 2 0.00
sec_cm_scramble_key_sideload 2 2 100.00
sram_ctrl_smoke 4.690s 2653.740us 2 2 100.00
sec_cm_tlul_fifo_ctr_redun 0 2 0.00
sram_ctrl_sec_cm 0.750s 2.561us 0 2 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 2 100.00
sram_ctrl_stress_all_with_rand_reset 168.220s 5857.497us 2 2 100.00