Simulation Results: uart

 
19/11/2025 16:06:30 sha: 241b623 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 90.12
  • line
  • 99.17
  • cond
  • 95.1
  • toggle
  • 91.55
  • fsm
  • None
  • branch
  • 97.44
  • assert
  • 97.12
  • group
  • 60.32
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.930s 407.964us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.760s 27.911us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.690s 51.983us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.240s 135.161us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.880s 102.838us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.730s 24.288us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.690s 51.983us 1 1 100.00
uart_csr_aliasing 0.880s 102.838us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 9.640s 33857.997us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.930s 407.964us 1 1 100.00
uart_tx_rx 9.640s 33857.997us 1 1 100.00
parity_error 2 2 100.00
uart_intr 5.610s 24498.913us 1 1 100.00
uart_rx_parity_err 53.410s 157142.515us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 9.640s 33857.997us 1 1 100.00
uart_intr 5.610s 24498.913us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 27.900s 23382.271us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 5.810s 4128.789us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 17.830s 32318.374us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 5.610s 24498.913us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 5.610s 24498.913us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 5.610s 24498.913us 1 1 100.00
perf 1 1 100.00
uart_perf 86.800s 9220.689us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.500s 3140.802us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.500s 3140.802us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 16.300s 73048.968us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.000s 3839.264us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.900s 1309.565us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 3.690s 6411.189us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 417.370s 106189.454us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 383.380s 320672.713us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.550s 38.836us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.660s 35.605us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.990s 49.369us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.990s 49.369us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.760s 27.911us 1 1 100.00
uart_csr_rw 0.690s 51.983us 1 1 100.00
uart_csr_aliasing 0.880s 102.838us 1 1 100.00
uart_same_csr_outstanding 0.770s 19.058us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.760s 27.911us 1 1 100.00
uart_csr_rw 0.690s 51.983us 1 1 100.00
uart_csr_aliasing 0.880s 102.838us 1 1 100.00
uart_same_csr_outstanding 0.770s 19.058us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.830s 41.464us 1 1 100.00
uart_tl_intg_err 1.070s 55.749us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.070s 55.749us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 18.710s 30051.187us 1 1 100.00