Simulation Results: ac_range_check

 
20/11/2025 16:06:59 sha: e8fccdb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • score
  • 96.65
  • block
  • 99.21
  • branch
  • 98.35
  • statement
  • 99.94
  • expression
  • 99.24
  • toggle
  • 81.0
  • fsm
  • None
  • assertion
  • 97.63
  • covergroup
  • 58.02
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 21.000s 783.359us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 31.000s 1146.840us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 3.000s 39.030us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 49.780us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 34.000s 24436.902us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 20.000s 17783.825us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 18.900us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 49.780us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 17783.825us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 3.000s 165.939us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 28.000s 7217.842us 1 1 100.00
stress_all 0 1 0.00
ac_range_check_stress_all 63.000s 1230.306us 0 1 0.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 14.302us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 24.338us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 4.000s 45.731us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 4.000s 45.731us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 3.000s 39.030us 1 1 100.00
ac_range_check_csr_rw 2.000s 49.780us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 17783.825us 1 1 100.00
ac_range_check_same_csr_outstanding 5.000s 182.075us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 3.000s 39.030us 1 1 100.00
ac_range_check_csr_rw 2.000s 49.780us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 17783.825us 1 1 100.00
ac_range_check_same_csr_outstanding 5.000s 182.075us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 772.347us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 772.347us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 772.347us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 772.347us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 91.000s 5558.740us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 2.000s 34.714us 1 1 100.00
ac_range_check_tl_intg_err 8.000s 668.309us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 295.000s 10528.048us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 26.000s 4156.455us 1 1 100.00