Simulation Results: clkmgr

 
20/11/2025 16:06:59 sha: e8fccdb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 72.46
  • line
  • 82.39
  • cond
  • 79.12
  • toggle
  • 99.62
  • fsm
  • 0.0
  • branch
  • 87.58
  • assert
  • 89.67
  • group
  • 68.83
Validation stages
V1
37.50%
V2
47.37%
V2S
52.94%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.160s 21.934us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.330s 37.150us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.860s 21.141us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.250s 50.188us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.930s 24.393us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.000s 23.851us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.860s 21.141us 0 1 0.00
clkmgr_csr_aliasing 0.930s 24.393us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.130s 40.580us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.180s 18.817us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.950s 18.298us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.160s 21.934us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.820s 5.445us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.880s 2.872us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.820s 5.445us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.220s 17.454us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.050s 53.425us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.530s 148.223us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.530s 148.223us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 1.330s 37.150us 1 1 100.00
clkmgr_csr_rw 0.860s 21.141us 0 1 0.00
clkmgr_csr_aliasing 0.930s 24.393us 0 1 0.00
clkmgr_same_csr_outstanding 0.970s 9.698us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 1.330s 37.150us 1 1 100.00
clkmgr_csr_rw 0.860s 21.141us 0 1 0.00
clkmgr_csr_aliasing 0.930s 24.393us 0 1 0.00
clkmgr_same_csr_outstanding 0.970s 9.698us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 2.450s 170.561us 1 1 100.00
clkmgr_tl_intg_err 0.890s 4.114us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 3.100s 319.011us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 3.100s 319.011us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 3.100s 319.011us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 3.100s 319.011us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.960s 11.800us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.890s 4.114us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.820s 5.445us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.880s 2.872us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 3.100s 319.011us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.070s 26.810us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.860s 21.141us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 2.450s 170.561us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.860s 21.141us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.860s 21.141us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 2.450s 170.561us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.820s 3.650us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.320s 20.149us 0 1 0.00