Simulation Results: csrng

 
20/11/2025 16:06:59 sha: e8fccdb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • score
  • 94.77
  • block
  • 96.79
  • branch
  • 92.12
  • statement
  • 97.77
  • expression
  • 94.98
  • toggle
  • 91.84
  • fsm
  • 84.85
  • assertion
  • 92.92
  • covergroup
  • 76.22
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 17.512us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 43.662us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 15.432us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 19.000s 521.246us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 5.000s 182.210us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 5.000s 321.856us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 15.432us 1 1 100.00
csrng_csr_aliasing 5.000s 182.210us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 122.205us 1 1 100.00
alerts 1 1 100.00
csrng_alert 17.000s 1152.232us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 24.899us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 35.000s 2660.516us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 35.000s 2660.516us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 396.000s 13497.738us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 22.438us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 39.401us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 74.741us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 74.741us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 43.662us 1 1 100.00
csrng_csr_rw 2.000s 15.432us 1 1 100.00
csrng_csr_aliasing 5.000s 182.210us 1 1 100.00
csrng_same_csr_outstanding 4.000s 165.728us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 43.662us 1 1 100.00
csrng_csr_rw 2.000s 15.432us 1 1 100.00
csrng_csr_aliasing 5.000s 182.210us 1 1 100.00
csrng_same_csr_outstanding 4.000s 165.728us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_tl_intg_err 2.000s 80.902us 1 1 100.00
csrng_sec_cm 3.000s 158.508us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_csr_rw 2.000s 15.432us 1 1 100.00
csrng_regwen 2.000s 13.372us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 17.000s 1152.232us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 396.000s 13497.738us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 122.205us 1 1 100.00
csrng_err 2.000s 24.899us 1 1 100.00
csrng_sec_cm 3.000s 158.508us 1 1 100.00
sec_cm_updrsp_fsm_sparse 3 3 100.00
csrng_intr 5.000s 122.205us 1 1 100.00
csrng_err 2.000s 24.899us 1 1 100.00
csrng_sec_cm 3.000s 158.508us 1 1 100.00
sec_cm_update_fsm_sparse 3 3 100.00
csrng_intr 5.000s 122.205us 1 1 100.00
csrng_err 2.000s 24.899us 1 1 100.00
csrng_sec_cm 3.000s 158.508us 1 1 100.00
sec_cm_blk_enc_fsm_sparse 3 3 100.00
csrng_intr 5.000s 122.205us 1 1 100.00
csrng_err 2.000s 24.899us 1 1 100.00
csrng_sec_cm 3.000s 158.508us 1 1 100.00
sec_cm_outblk_fsm_sparse 3 3 100.00
csrng_intr 5.000s 122.205us 1 1 100.00
csrng_err 2.000s 24.899us 1 1 100.00
csrng_sec_cm 3.000s 158.508us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 122.205us 1 1 100.00
csrng_err 2.000s 24.899us 1 1 100.00
csrng_sec_cm 3.000s 158.508us 1 1 100.00
sec_cm_drbg_upd_ctr_redun 3 3 100.00
csrng_intr 5.000s 122.205us 1 1 100.00
csrng_err 2.000s 24.899us 1 1 100.00
csrng_sec_cm 3.000s 158.508us 1 1 100.00
sec_cm_drbg_gen_ctr_redun 3 3 100.00
csrng_intr 5.000s 122.205us 1 1 100.00
csrng_err 2.000s 24.899us 1 1 100.00
csrng_sec_cm 3.000s 158.508us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 17.000s 1152.232us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 122.205us 1 1 100.00
csrng_err 2.000s 24.899us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 396.000s 13497.738us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 17.000s 1152.232us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 2.000s 80.902us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 122.205us 1 1 100.00
csrng_err 2.000s 24.899us 1 1 100.00
csrng_sec_cm 3.000s 158.508us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 122.205us 1 1 100.00
csrng_err 2.000s 24.899us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 122.205us 1 1 100.00
csrng_err 2.000s 24.899us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 122.205us 1 1 100.00
csrng_err 2.000s 24.899us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 122.205us 1 1 100.00
csrng_err 2.000s 24.899us 1 1 100.00
csrng_sec_cm 3.000s 158.508us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 122.205us 1 1 100.00
csrng_err 2.000s 24.899us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
csrng_stress_all_with_rand_reset 215.000s 8620.197us 1 1 100.00