Simulation Results: dma

 
20/11/2025 16:06:59 sha: e8fccdb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • score
  • 88.85
  • block
  • 97.38
  • branch
  • 95.83
  • statement
  • 96.89
  • expression
  • 92.62
  • toggle
  • 83.12
  • fsm
  • 92.96
  • assertion
  • 95.97
  • covergroup
  • 62.0
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 6.000s 968.303us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 6.000s 306.413us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 581.649us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 56.093us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 13.971us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 9.000s 1714.080us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 4.000s 592.471us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 76.876us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 13.971us 1 1 100.00
dma_csr_aliasing 4.000s 592.471us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 51.000s 15373.450us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 788.000s 69213.396us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 473.000s 212241.297us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 473.000s 212241.297us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 788.000s 69213.396us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 141.000s 14003.067us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 473.000s 212241.297us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 7.000s 980.557us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 108.000s 10029.049us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 13.319us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 21.828us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 103.795us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 103.795us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 56.093us 1 1 100.00
dma_csr_rw 1.000s 13.971us 1 1 100.00
dma_csr_aliasing 4.000s 592.471us 1 1 100.00
dma_same_csr_outstanding 2.000s 194.205us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 56.093us 1 1 100.00
dma_csr_rw 1.000s 13.971us 1 1 100.00
dma_csr_aliasing 4.000s 592.471us 1 1 100.00
dma_same_csr_outstanding 2.000s 194.205us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 18.000s 267.624us 1 1 100.00
dma_generic_stress 141.000s 14003.067us 1 1 100.00
dma_handshake_stress 473.000s 212241.297us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 11.000s 2489.752us 1 1 100.00
tl_intg_err 2 2 100.00
dma_sec_cm 2.000s 20.074us 1 1 100.00
dma_tl_intg_err 3.000s 200.158us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 62.000s 71424.930us 1 1 100.00
dma_longer_transfer 4.000s 178.890us 1 1 100.00
dma_stress_all_with_rand_reset 10.000s 2562.656us 0 1 0.00