Simulation Results: edn

 
20/11/2025 16:06:59 sha: e8fccdb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 82.22
  • line
  • 97.79
  • cond
  • 84.8
  • toggle
  • 79.73
  • fsm
  • 51.74
  • branch
  • 92.38
  • assert
  • 96.0
  • group
  • 73.09
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 56.421us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.020s 45.017us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.960s 57.715us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.050s 509.870us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.560s 21.557us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.020s 52.031us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.960s 57.715us 1 1 100.00
edn_csr_aliasing 1.560s 21.557us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 3.450s 381.435us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 3.450s 381.435us 1 1 100.00
genbits 1 1 100.00
edn_genbits 3.450s 381.435us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.190s 27.342us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.210s 24.609us 1 1 100.00
errs 1 1 100.00
edn_err 0.880s 64.443us 1 1 100.00
disable 2 2 100.00
edn_disable 1.060s 24.194us 1 1 100.00
edn_disable_auto_req_mode 1.510s 407.815us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.390s 245.852us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.910s 100.817us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.890s 51.370us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.720s 112.408us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.720s 112.408us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.020s 45.017us 1 1 100.00
edn_csr_rw 0.960s 57.715us 1 1 100.00
edn_csr_aliasing 1.560s 21.557us 1 1 100.00
edn_same_csr_outstanding 1.220s 82.277us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.020s 45.017us 1 1 100.00
edn_csr_rw 0.960s 57.715us 1 1 100.00
edn_csr_aliasing 1.560s 21.557us 1 1 100.00
edn_same_csr_outstanding 1.220s 82.277us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.500s 86.496us 1 1 100.00
edn_sec_cm 5.840s 1790.298us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.190s 18.212us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.210s 24.609us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.840s 1790.298us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.840s 1790.298us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.840s 1790.298us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.840s 1790.298us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.210s 24.609us 1 1 100.00
edn_sec_cm 5.840s 1790.298us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.210s 24.609us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.500s 86.496us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00