Simulation Results: hmac

 
20/11/2025 16:06:59 sha: e8fccdb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 90.04
  • line
  • 99.63
  • cond
  • 96.18
  • toggle
  • 100.0
  • fsm
  • 94.12
  • branch
  • 99.17
  • assert
  • 96.9
  • group
  • 44.28
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 7.840s 882.452us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.930s 110.413us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.870s 17.103us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.960s 3886.147us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.080s 113.091us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.590s 155.079us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.870s 17.103us 1 1 100.00
hmac_csr_aliasing 4.080s 113.091us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 34.170s 32084.263us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 52.790s 5085.100us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 7.900s 181.128us 1 1 100.00
hmac_test_sha384_vectors 384.960s 49149.636us 1 1 100.00
hmac_test_sha512_vectors 418.860s 23526.848us 1 1 100.00
hmac_test_hmac256_vectors 10.030s 1184.977us 1 1 100.00
hmac_test_hmac384_vectors 8.080s 990.290us 1 1 100.00
hmac_test_hmac512_vectors 12.940s 477.467us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 10.080s 3361.539us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 299.660s 9684.665us 1 1 100.00
error 1 1 100.00
hmac_error 11.190s 277.687us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 102.160s 5488.370us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 7.840s 882.452us 1 1 100.00
hmac_long_msg 34.170s 32084.263us 1 1 100.00
hmac_back_pressure 52.790s 5085.100us 1 1 100.00
hmac_datapath_stress 299.660s 9684.665us 1 1 100.00
hmac_burst_wr 10.080s 3361.539us 1 1 100.00
hmac_stress_all 733.660s 24642.434us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 7.840s 882.452us 1 1 100.00
hmac_long_msg 34.170s 32084.263us 1 1 100.00
hmac_back_pressure 52.790s 5085.100us 1 1 100.00
hmac_datapath_stress 299.660s 9684.665us 1 1 100.00
hmac_wipe_secret 102.160s 5488.370us 1 1 100.00
hmac_test_sha256_vectors 7.900s 181.128us 1 1 100.00
hmac_test_sha384_vectors 384.960s 49149.636us 1 1 100.00
hmac_test_sha512_vectors 418.860s 23526.848us 1 1 100.00
hmac_test_hmac256_vectors 10.030s 1184.977us 1 1 100.00
hmac_test_hmac384_vectors 8.080s 990.290us 1 1 100.00
hmac_test_hmac512_vectors 12.940s 477.467us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 7.840s 882.452us 1 1 100.00
hmac_long_msg 34.170s 32084.263us 1 1 100.00
hmac_back_pressure 52.790s 5085.100us 1 1 100.00
hmac_datapath_stress 299.660s 9684.665us 1 1 100.00
hmac_burst_wr 10.080s 3361.539us 1 1 100.00
hmac_error 11.190s 277.687us 1 1 100.00
hmac_wipe_secret 102.160s 5488.370us 1 1 100.00
hmac_test_sha256_vectors 7.900s 181.128us 1 1 100.00
hmac_test_sha384_vectors 384.960s 49149.636us 1 1 100.00
hmac_test_sha512_vectors 418.860s 23526.848us 1 1 100.00
hmac_test_hmac256_vectors 10.030s 1184.977us 1 1 100.00
hmac_test_hmac384_vectors 8.080s 990.290us 1 1 100.00
hmac_test_hmac512_vectors 12.940s 477.467us 1 1 100.00
hmac_stress_all 733.660s 24642.434us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 733.660s 24642.434us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.740s 12.939us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.760s 12.634us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.010s 193.570us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.010s 193.570us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.930s 110.413us 1 1 100.00
hmac_csr_rw 0.870s 17.103us 1 1 100.00
hmac_csr_aliasing 4.080s 113.091us 1 1 100.00
hmac_same_csr_outstanding 1.070s 21.535us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.930s 110.413us 1 1 100.00
hmac_csr_rw 0.870s 17.103us 1 1 100.00
hmac_csr_aliasing 4.080s 113.091us 1 1 100.00
hmac_same_csr_outstanding 1.070s 21.535us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 1.490s 108.215us 1 1 100.00
hmac_sec_cm 1.110s 493.013us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.490s 108.215us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 7.840s 882.452us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.060s 1684.067us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 3.870s 676.912us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 6.370s 743.638us 1 1 100.00