| host_error_intr |
0 |
1 |
0.00 |
|
i2c_host_error_intr |
3.760s |
476.536us |
0 |
1 |
0.00
|
| host_stress_all |
0 |
1 |
0.00 |
|
i2c_host_stress_all |
869.270s |
15959.553us |
0 |
1 |
0.00
|
| host_maxperf |
1 |
1 |
100.00 |
|
i2c_host_perf |
126.880s |
18033.500us |
1 |
1 |
100.00
|
| host_override |
1 |
1 |
100.00 |
|
i2c_host_override |
0.950s |
43.952us |
1 |
1 |
100.00
|
| host_fifo_watermark |
1 |
1 |
100.00 |
|
i2c_host_fifo_watermark |
108.640s |
2757.810us |
1 |
1 |
100.00
|
| host_fifo_overflow |
1 |
1 |
100.00 |
|
i2c_host_fifo_overflow |
101.130s |
2250.737us |
1 |
1 |
100.00
|
| host_fifo_reset |
3 |
3 |
100.00 |
|
i2c_host_fifo_reset_fmt |
1.060s |
311.923us |
1 |
1 |
100.00
|
|
i2c_host_fifo_fmt_empty |
8.720s |
579.253us |
1 |
1 |
100.00
|
|
i2c_host_fifo_reset_rx |
4.980s |
147.038us |
1 |
1 |
100.00
|
| host_fifo_full |
1 |
1 |
100.00 |
|
i2c_host_fifo_full |
38.290s |
15080.215us |
1 |
1 |
100.00
|
| host_timeout |
1 |
1 |
100.00 |
|
i2c_host_stretch_timeout |
19.150s |
1157.061us |
1 |
1 |
100.00
|
| i2c_host_mode_toggle |
0 |
1 |
0.00 |
|
i2c_host_mode_toggle |
1.890s |
269.177us |
0 |
1 |
0.00
|
| target_glitch |
0 |
1 |
0.00 |
|
i2c_target_glitch |
2.060s |
1876.669us |
0 |
1 |
0.00
|
| target_stress_all |
1 |
1 |
100.00 |
|
i2c_target_stress_all |
71.810s |
25389.988us |
1 |
1 |
100.00
|
| target_maxperf |
1 |
1 |
100.00 |
|
i2c_target_perf |
3.020s |
10084.651us |
1 |
1 |
100.00
|
| target_fifo_empty |
2 |
2 |
100.00 |
|
i2c_target_stress_rd |
11.330s |
6807.722us |
1 |
1 |
100.00
|
|
i2c_target_intr_smoke |
4.640s |
2503.514us |
1 |
1 |
100.00
|
| target_fifo_reset |
2 |
2 |
100.00 |
|
i2c_target_fifo_reset_acq |
1.870s |
235.168us |
1 |
1 |
100.00
|
|
i2c_target_fifo_reset_tx |
1.670s |
477.973us |
1 |
1 |
100.00
|
| target_fifo_full |
3 |
3 |
100.00 |
|
i2c_target_stress_wr |
45.880s |
40950.701us |
1 |
1 |
100.00
|
|
i2c_target_stress_rd |
11.330s |
6807.722us |
1 |
1 |
100.00
|
|
i2c_target_intr_stress_wr |
7.170s |
4737.764us |
1 |
1 |
100.00
|
| target_timeout |
1 |
1 |
100.00 |
|
i2c_target_timeout |
7.970s |
1403.177us |
1 |
1 |
100.00
|
| target_clock_stretch |
1 |
1 |
100.00 |
|
i2c_target_stretch |
3.020s |
2718.884us |
1 |
1 |
100.00
|
| bad_address |
1 |
1 |
100.00 |
|
i2c_target_bad_addr |
5.870s |
3250.654us |
1 |
1 |
100.00
|
| target_mode_glitch |
0 |
1 |
0.00 |
|
i2c_target_hrst |
5.460s |
10055.475us |
0 |
1 |
0.00
|
| target_fifo_watermark |
2 |
2 |
100.00 |
|
i2c_target_fifo_watermarks_acq |
1.830s |
1938.436us |
1 |
1 |
100.00
|
|
i2c_target_fifo_watermarks_tx |
1.180s |
898.034us |
1 |
1 |
100.00
|
| host_mode_config_perf |
2 |
2 |
100.00 |
|
i2c_host_perf |
126.880s |
18033.500us |
1 |
1 |
100.00
|
|
i2c_host_perf_precise |
1.290s |
121.740us |
1 |
1 |
100.00
|
| host_mode_clock_stretching |
1 |
1 |
100.00 |
|
i2c_host_stretch_timeout |
19.150s |
1157.061us |
1 |
1 |
100.00
|
| target_mode_tx_stretch_ctrl |
1 |
1 |
100.00 |
|
i2c_target_tx_stretch_ctrl |
2.460s |
138.893us |
1 |
1 |
100.00
|
| target_mode_nack_generation |
2 |
3 |
66.67 |
|
i2c_target_nack_acqfull |
2.560s |
1195.904us |
1 |
1 |
100.00
|
|
i2c_target_nack_acqfull_addr |
1.790s |
1050.165us |
1 |
1 |
100.00
|
|
i2c_target_nack_txstretch |
1.560s |
606.718us |
0 |
1 |
0.00
|
| host_mode_halt_on_nak |
1 |
1 |
100.00 |
|
i2c_host_may_nack |
2.780s |
1347.606us |
1 |
1 |
100.00
|
| target_mode_smbus_maxlen |
1 |
1 |
100.00 |
|
i2c_target_smbus_maxlen |
1.510s |
803.955us |
1 |
1 |
100.00
|
| alert_test |
1 |
1 |
100.00 |
|
i2c_alert_test |
0.810s |
42.127us |
1 |
1 |
100.00
|
| intr_test |
1 |
1 |
100.00 |
|
i2c_intr_test |
0.740s |
21.353us |
1 |
1 |
100.00
|
| tl_d_oob_addr_access |
1 |
1 |
100.00 |
|
i2c_tl_errors |
2.250s |
122.597us |
1 |
1 |
100.00
|
| tl_d_illegal_access |
1 |
1 |
100.00 |
|
i2c_tl_errors |
2.250s |
122.597us |
1 |
1 |
100.00
|
| tl_d_outstanding_access |
4 |
4 |
100.00 |
|
i2c_csr_hw_reset |
0.680s |
25.415us |
1 |
1 |
100.00
|
|
i2c_csr_rw |
0.860s |
27.259us |
1 |
1 |
100.00
|
|
i2c_csr_aliasing |
1.170s |
179.913us |
1 |
1 |
100.00
|
|
i2c_same_csr_outstanding |
0.890s |
90.245us |
1 |
1 |
100.00
|
| tl_d_partial_access |
4 |
4 |
100.00 |
|
i2c_csr_hw_reset |
0.680s |
25.415us |
1 |
1 |
100.00
|
|
i2c_csr_rw |
0.860s |
27.259us |
1 |
1 |
100.00
|
|
i2c_csr_aliasing |
1.170s |
179.913us |
1 |
1 |
100.00
|
|
i2c_same_csr_outstanding |
0.890s |
90.245us |
1 |
1 |
100.00
|