Simulation Results: rom_ctrl

 
20/11/2025 16:06:59 sha: e8fccdb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 94.75
  • line
  • 99.32
  • cond
  • 97.77
  • toggle
  • 99.97
  • fsm
  • 73.33
  • branch
  • 98.91
  • assert
  • 96.8
  • group
  • 97.14
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 6.920s 311.411us 2 2 100.00
csr_hw_reset 2 2 100.00
rom_ctrl_csr_hw_reset 8.870s 3140.974us 2 2 100.00
csr_rw 2 2 100.00
rom_ctrl_csr_rw 6.930s 586.326us 2 2 100.00
csr_bit_bash 2 2 100.00
rom_ctrl_csr_bit_bash 6.600s 214.893us 2 2 100.00
csr_aliasing 2 2 100.00
rom_ctrl_csr_aliasing 8.090s 2785.758us 2 2 100.00
csr_mem_rw_with_rand_reset 2 2 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.060s 954.733us 2 2 100.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
rom_ctrl_csr_rw 6.930s 586.326us 2 2 100.00
rom_ctrl_csr_aliasing 8.090s 2785.758us 2 2 100.00
mem_walk 2 2 100.00
rom_ctrl_mem_walk 6.580s 1491.398us 2 2 100.00
mem_partial_access 2 2 100.00
rom_ctrl_mem_partial_access 6.270s 212.370us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 6.790s 768.136us 2 2 100.00
stress_all 2 2 100.00
rom_ctrl_stress_all 21.010s 591.003us 2 2 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 14.020s 2198.093us 2 2 100.00
alert_test 2 2 100.00
rom_ctrl_alert_test 6.000s 210.879us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
rom_ctrl_tl_errors 7.860s 726.019us 2 2 100.00
tl_d_illegal_access 2 2 100.00
rom_ctrl_tl_errors 7.860s 726.019us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
rom_ctrl_csr_hw_reset 8.870s 3140.974us 2 2 100.00
rom_ctrl_csr_rw 6.930s 586.326us 2 2 100.00
rom_ctrl_csr_aliasing 8.090s 2785.758us 2 2 100.00
rom_ctrl_same_csr_outstanding 6.090s 205.335us 2 2 100.00
tl_d_partial_access 8 8 100.00
rom_ctrl_csr_hw_reset 8.870s 3140.974us 2 2 100.00
rom_ctrl_csr_rw 6.930s 586.326us 2 2 100.00
rom_ctrl_csr_aliasing 8.090s 2785.758us 2 2 100.00
rom_ctrl_same_csr_outstanding 6.090s 205.335us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.010s 2203.813us 2 2 100.00
passthru_mem_tl_intg_err 2 2 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.550s 3262.424us 2 2 100.00
tl_intg_err 3 4 75.00
rom_ctrl_sec_cm 461.520s 1315.148us 1 2 50.00
rom_ctrl_tl_intg_err 53.600s 429.553us 2 2 100.00
prim_fsm_check 1 2 50.00
rom_ctrl_sec_cm 461.520s 1315.148us 1 2 50.00
prim_count_check 1 2 50.00
rom_ctrl_sec_cm 461.520s 1315.148us 1 2 50.00
sec_cm_checker_ctr_consistency 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.010s 2203.813us 2 2 100.00
sec_cm_checker_ctrl_flow_consistency 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.010s 2203.813us 2 2 100.00
sec_cm_checker_fsm_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.010s 2203.813us 2 2 100.00
sec_cm_compare_ctrl_flow_consistency 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.010s 2203.813us 2 2 100.00
sec_cm_compare_ctr_consistency 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.010s 2203.813us 2 2 100.00
sec_cm_compare_ctr_redun 1 2 50.00
rom_ctrl_sec_cm 461.520s 1315.148us 1 2 50.00
sec_cm_fsm_sparse 1 2 50.00
rom_ctrl_sec_cm 461.520s 1315.148us 1 2 50.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 6.920s 311.411us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 6.920s 311.411us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 6.920s 311.411us 2 2 100.00
sec_cm_bus_integrity 2 2 100.00
rom_ctrl_tl_intg_err 53.600s 429.553us 2 2 100.00
sec_cm_bus_local_esc 4 4 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.010s 2203.813us 2 2 100.00
rom_ctrl_kmac_err_chk 14.020s 2198.093us 2 2 100.00
sec_cm_mux_mubi 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.010s 2203.813us 2 2 100.00
sec_cm_mux_consistency 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.010s 2203.813us 2 2 100.00
sec_cm_ctrl_redun 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.010s 2203.813us 2 2 100.00
sec_cm_ctrl_mem_integrity 2 2 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.550s 3262.424us 2 2 100.00
sec_cm_tlul_fifo_ctr_redun 1 2 50.00
rom_ctrl_sec_cm 461.520s 1315.148us 1 2 50.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 2 100.00
rom_ctrl_stress_all_with_rand_reset 131.890s 6318.539us 2 2 100.00