Simulation Results: rv_dm

 
20/11/2025 16:06:59 sha: e8fccdb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 74.32
  • line
  • 90.48
  • cond
  • 72.84
  • toggle
  • 70.41
  • fsm
  • 56.25
  • branch
  • 74.57
  • assert
  • 94.93
  • group
  • 60.78
Validation stages
V1
93.55%
V2
64.29%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 1.840s 1493.458us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 0.970s 1391.081us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 1.280s 289.283us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 7.620s 6330.684us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 5.160s 2160.566us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 13.550s 11466.042us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 11.700s 12460.939us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 64.370s 95250.913us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 53.700s 52334.535us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 1.070s 678.692us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 1.450s 365.149us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 1.140s 185.921us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 1.930s 338.248us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 1.920s 666.545us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 1.440s 390.269us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 0.930s 86.484us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 2.880s 1040.060us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 1.070s 678.692us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 1.600s 415.317us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 2.340s 873.542us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 1.140s 185.921us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 1.400s 95.746us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 2.110s 167.130us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 2.310s 272.728us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 28.800s 3769.884us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 22.830s 13328.727us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
rv_dm_csr_mem_rw_with_rand_reset 0.980s 29.436us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 22.830s 13328.727us 1 1 100.00
rv_dm_csr_rw 2.310s 272.728us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 0.750s 44.619us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 1.060s 175.929us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 1.840s 1493.458us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 0.920s 175.385us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 1.110s 144.339us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 1.020s 153.116us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 1.090s 447.334us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 286.320s 300000.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 146.860s 300000.000us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 317.920s 300000.000us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 294.740s 300000.000us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 0.990s 79.122us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 4.260s 4929.475us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 1.160s 698.741us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 0.930s 40.798us 0 1 0.00
tap_ctrl_transitions 1 2 50.00
rv_dm_tap_fsm_rand_reset 1.290s 99.528us 0 1 0.00
rv_dm_tap_fsm 25.260s 10424.163us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 1.040s 148.139us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 1.040s 224.166us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 0.900s 57.657us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
rv_dm_tl_errors 1.820s 290.718us 0 1 0.00
tl_d_illegal_access 0 1 0.00
rv_dm_tl_errors 1.820s 290.718us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 22.830s 13328.727us 1 1 100.00
rv_dm_csr_hw_reset 2.110s 167.130us 1 1 100.00
rv_dm_csr_rw 2.310s 272.728us 1 1 100.00
rv_dm_same_csr_outstanding 5.090s 895.291us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 22.830s 13328.727us 1 1 100.00
rv_dm_csr_hw_reset 2.110s 167.130us 1 1 100.00
rv_dm_csr_rw 2.310s 272.728us 1 1 100.00
rv_dm_same_csr_outstanding 5.090s 895.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_tl_intg_err 8.290s 4335.463us 1 1 100.00
rv_dm_sec_cm 1.990s 517.959us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 8.290s 4335.463us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 4.260s 4929.475us 1 1 100.00
rv_dm_debug_disabled 1.320s 69.109us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 4.260s 4929.475us 1 1 100.00
rv_dm_debug_disabled 1.320s 69.109us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 1.840s 1493.458us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 1.460s 310.160us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.980s 66.736us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.980s 66.736us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 1.460s 310.160us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 0.890s 33.795us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 148.850s 300000.000us 0 1 0.00