Simulation Results: spi_device

 
20/11/2025 16:06:59 sha: e8fccdb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 89.88
  • line
  • 99.04
  • cond
  • 96.09
  • toggle
  • 83.54
  • fsm
  • 89.36
  • branch
  • 98.25
  • assert
  • 94.3
  • group
  • 68.6
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 266.090s 50055.240us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.990s 50.914us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.360s 28.002us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 12.710s 4099.769us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 10.600s 208.598us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.630s 128.172us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.360s 28.002us 1 1 100.00
spi_device_csr_aliasing 10.600s 208.598us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.950s 61.609us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.530s 17.706us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.090s 16.744us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.830s 5.064us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.810s 7.980us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.350s 69.972us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.350s 69.972us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.690s 365.187us 1 1 100.00
spi_device_tpm_sts_read 1.000s 50.020us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 16.500s 2013.178us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 8.330s 6613.345us 1 1 100.00
spi_device_flash_all 162.830s 40150.945us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 9.880s 16239.521us 1 1 100.00
spi_device_flash_all 162.830s 40150.945us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 9.880s 16239.521us 1 1 100.00
spi_device_flash_all 162.830s 40150.945us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 162.830s 40150.945us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 8.750s 1584.655us 1 1 100.00
spi_device_flash_all 162.830s 40150.945us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 8.750s 1584.655us 1 1 100.00
spi_device_flash_all 162.830s 40150.945us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 8.750s 1584.655us 1 1 100.00
spi_device_flash_all 162.830s 40150.945us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 8.750s 1584.655us 1 1 100.00
spi_device_flash_all 162.830s 40150.945us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 8.750s 1584.655us 1 1 100.00
spi_device_flash_all 162.830s 40150.945us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 6.860s 1681.709us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 53.640s 13184.869us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 53.640s 13184.869us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 53.640s 13184.869us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 24.970s 2913.948us 1 1 100.00
spi_device_read_buffer_direct 3.170s 338.358us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 53.640s 13184.869us 1 1 100.00
spi_device_flash_all 162.830s 40150.945us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 162.830s 40150.945us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 162.830s 40150.945us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 1.940s 64.525us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 1.940s 64.525us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 266.090s 50055.240us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 44.940s 18376.061us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 140.490s 83901.946us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.880s 30.324us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.840s 40.123us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.020s 53.986us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.020s 53.986us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.990s 50.914us 1 1 100.00
spi_device_csr_rw 1.360s 28.002us 1 1 100.00
spi_device_csr_aliasing 10.600s 208.598us 1 1 100.00
spi_device_same_csr_outstanding 2.020s 104.016us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.990s 50.914us 1 1 100.00
spi_device_csr_rw 1.360s 28.002us 1 1 100.00
spi_device_csr_aliasing 10.600s 208.598us 1 1 100.00
spi_device_same_csr_outstanding 2.020s 104.016us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 4.670s 147.296us 1 1 100.00
spi_device_sec_cm 1.540s 591.606us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 4.670s 147.296us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 22.190s 17346.279us 1 1 100.00