Simulation Results: sram_ctrl

 
20/11/2025 16:06:59 sha: e8fccdb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 94.03
  • line
  • 98.33
  • cond
  • 91.55
  • toggle
  • 90.59
  • fsm
  • 90.48
  • branch
  • 95.71
  • assert
  • 95.79
  • group
  • 95.73
Validation stages
V1
100.00%
V2
100.00%
V2S
70.83%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
sram_ctrl_smoke 15.370s 2094.352us 2 2 100.00
csr_hw_reset 2 2 100.00
sram_ctrl_csr_hw_reset 0.810s 15.105us 2 2 100.00
csr_rw 2 2 100.00
sram_ctrl_csr_rw 0.710s 36.025us 2 2 100.00
csr_bit_bash 2 2 100.00
sram_ctrl_csr_bit_bash 1.670s 118.917us 2 2 100.00
csr_aliasing 2 2 100.00
sram_ctrl_csr_aliasing 0.910s 55.268us 2 2 100.00
csr_mem_rw_with_rand_reset 2 2 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.230s 1312.002us 2 2 100.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
sram_ctrl_csr_rw 0.710s 36.025us 2 2 100.00
sram_ctrl_csr_aliasing 0.910s 55.268us 2 2 100.00
mem_walk 2 2 100.00
sram_ctrl_mem_walk 127.110s 41346.336us 2 2 100.00
mem_partial_access 2 2 100.00
sram_ctrl_mem_partial_access 108.660s 5222.163us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 2 2 100.00
sram_ctrl_multiple_keys 563.260s 103764.483us 2 2 100.00
stress_pipeline 2 2 100.00
sram_ctrl_stress_pipeline 284.990s 3944.399us 2 2 100.00
bijection 2 2 100.00
sram_ctrl_bijection 992.820s 79965.877us 2 2 100.00
access_during_key_req 2 2 100.00
sram_ctrl_access_during_key_req 984.250s 21102.651us 2 2 100.00
lc_escalation 2 2 100.00
sram_ctrl_lc_escalation 6.540s 3207.521us 2 2 100.00
executable 2 2 100.00
sram_ctrl_executable 859.520s 84248.777us 2 2 100.00
partial_access 4 4 100.00
sram_ctrl_partial_access 9.260s 822.890us 2 2 100.00
sram_ctrl_partial_access_b2b 244.150s 26262.251us 2 2 100.00
max_throughput 6 6 100.00
sram_ctrl_max_throughput 31.850s 478.247us 2 2 100.00
sram_ctrl_throughput_w_partial_write 51.030s 5577.231us 2 2 100.00
sram_ctrl_throughput_w_readback 25.090s 10246.222us 2 2 100.00
regwen 2 2 100.00
sram_ctrl_regwen 468.370s 3634.280us 2 2 100.00
ram_cfg 2 2 100.00
sram_ctrl_ram_cfg 2.180s 1352.682us 2 2 100.00
stress_all 2 2 100.00
sram_ctrl_stress_all 3382.110s 809436.007us 2 2 100.00
alert_test 2 2 100.00
sram_ctrl_alert_test 0.720s 32.230us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
sram_ctrl_tl_errors 3.590s 144.613us 2 2 100.00
tl_d_illegal_access 2 2 100.00
sram_ctrl_tl_errors 3.590s 144.613us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
sram_ctrl_csr_hw_reset 0.810s 15.105us 2 2 100.00
sram_ctrl_csr_rw 0.710s 36.025us 2 2 100.00
sram_ctrl_csr_aliasing 0.910s 55.268us 2 2 100.00
sram_ctrl_same_csr_outstanding 0.730s 70.303us 2 2 100.00
tl_d_partial_access 8 8 100.00
sram_ctrl_csr_hw_reset 0.810s 15.105us 2 2 100.00
sram_ctrl_csr_rw 0.710s 36.025us 2 2 100.00
sram_ctrl_csr_aliasing 0.910s 55.268us 2 2 100.00
sram_ctrl_same_csr_outstanding 0.730s 70.303us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 2 2 100.00
sram_ctrl_passthru_mem_tl_intg_err 16.630s 3740.493us 2 2 100.00
tl_intg_err 2 4 50.00
sram_ctrl_sec_cm 0.750s 7.300us 0 2 0.00
sram_ctrl_tl_intg_err 2.430s 230.788us 2 2 100.00
prim_count_check 0 2 0.00
sram_ctrl_sec_cm 0.750s 7.300us 0 2 0.00
sec_cm_bus_integrity 2 2 100.00
sram_ctrl_tl_intg_err 2.430s 230.788us 2 2 100.00
sec_cm_ctrl_config_regwen 2 2 100.00
sram_ctrl_regwen 468.370s 3634.280us 2 2 100.00
sec_cm_readback_config_regwen 2 2 100.00
sram_ctrl_regwen 468.370s 3634.280us 2 2 100.00
sec_cm_exec_config_regwen 2 2 100.00
sram_ctrl_csr_rw 0.710s 36.025us 2 2 100.00
sec_cm_exec_config_mubi 2 2 100.00
sram_ctrl_executable 859.520s 84248.777us 2 2 100.00
sec_cm_exec_intersig_mubi 2 2 100.00
sram_ctrl_executable 859.520s 84248.777us 2 2 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
sram_ctrl_executable 859.520s 84248.777us 2 2 100.00
sec_cm_lc_escalate_en_intersig_mubi 2 2 100.00
sram_ctrl_lc_escalation 6.540s 3207.521us 2 2 100.00
sec_cm_prim_ram_ctrl_mubi 2 2 100.00
sram_ctrl_mubi_enc_err 3.670s 1663.021us 2 2 100.00
sec_cm_mem_integrity 2 2 100.00
sram_ctrl_passthru_mem_tl_intg_err 16.630s 3740.493us 2 2 100.00
sec_cm_mem_readback 0 2 0.00
sram_ctrl_readback_err 4.170s 7308.961us 0 2 0.00
sec_cm_mem_scramble 2 2 100.00
sram_ctrl_smoke 15.370s 2094.352us 2 2 100.00
sec_cm_addr_scramble 2 2 100.00
sram_ctrl_smoke 15.370s 2094.352us 2 2 100.00
sec_cm_instr_bus_lc_gated 2 2 100.00
sram_ctrl_executable 859.520s 84248.777us 2 2 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 2 0.00
sram_ctrl_sec_cm 0.750s 7.300us 0 2 0.00
sec_cm_key_global_esc 2 2 100.00
sram_ctrl_lc_escalation 6.540s 3207.521us 2 2 100.00
sec_cm_key_local_esc 0 2 0.00
sram_ctrl_sec_cm 0.750s 7.300us 0 2 0.00
sec_cm_init_ctr_redun 0 2 0.00
sram_ctrl_sec_cm 0.750s 7.300us 0 2 0.00
sec_cm_scramble_key_sideload 2 2 100.00
sram_ctrl_smoke 15.370s 2094.352us 2 2 100.00
sec_cm_tlul_fifo_ctr_redun 0 2 0.00
sram_ctrl_sec_cm 0.750s 7.300us 0 2 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 2 100.00
sram_ctrl_stress_all_with_rand_reset 50.290s 292.845us 2 2 100.00