Simulation Results: uart

 
20/11/2025 16:06:59 sha: e8fccdb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 88.33
  • line
  • 98.86
  • cond
  • 91.72
  • toggle
  • 91.55
  • fsm
  • None
  • branch
  • 96.27
  • assert
  • 97.12
  • group
  • 54.46
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.270s 303.921us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.750s 16.014us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.640s 41.352us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.270s 137.060us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.630s 62.913us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.630s 60.201us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.640s 41.352us 1 1 100.00
uart_csr_aliasing 0.630s 62.913us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 49.310s 51365.002us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.270s 303.921us 1 1 100.00
uart_tx_rx 49.310s 51365.002us 1 1 100.00
parity_error 2 2 100.00
uart_intr 99.850s 83776.796us 1 1 100.00
uart_rx_parity_err 35.270s 52882.484us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 49.310s 51365.002us 1 1 100.00
uart_intr 99.850s 83776.796us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 78.920s 213078.465us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 166.550s 145950.744us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 18.780s 79476.457us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 99.850s 83776.796us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 99.850s 83776.796us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 99.850s 83776.796us 1 1 100.00
perf 1 1 100.00
uart_perf 492.540s 17694.584us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.380s 2186.274us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.380s 2186.274us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 8.670s 50725.404us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 31.670s 28176.929us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 7.730s 7284.015us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 9.330s 2110.548us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 81.410s 79953.068us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 292.820s 112502.817us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.730s 15.679us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.740s 22.850us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.330s 148.112us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.330s 148.112us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.750s 16.014us 1 1 100.00
uart_csr_rw 0.640s 41.352us 1 1 100.00
uart_csr_aliasing 0.630s 62.913us 1 1 100.00
uart_same_csr_outstanding 0.790s 41.962us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.750s 16.014us 1 1 100.00
uart_csr_rw 0.640s 41.352us 1 1 100.00
uart_csr_aliasing 0.630s 62.913us 1 1 100.00
uart_same_csr_outstanding 0.790s 41.962us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.100s 240.035us 1 1 100.00
uart_tl_intg_err 1.390s 98.433us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.390s 98.433us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 19.870s 2872.967us 1 1 100.00