| V1 |
|
100.00% |
| V2 |
|
83.33% |
| V2S |
|
88.89% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 29.930s | 773.673us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 3.330s | 79.884us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| alert_handler_csr_rw | 7.820s | 246.741us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 176.190s | 1852.342us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 200.920s | 14879.940us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 10.780s | 371.357us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| alert_handler_csr_rw | 7.820s | 246.741us | 1 | 1 | 100.00 | |
| alert_handler_csr_aliasing | 200.920s | 14879.940us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 1 | 1 | 100.00 | |||
| alert_handler_esc_alert_accum | 20.400s | 880.606us | 1 | 1 | 100.00 | |
| esc_timeout | 1 | 1 | 100.00 | |||
| alert_handler_esc_intr_timeout | 4.210s | 46.160us | 1 | 1 | 100.00 | |
| entropy | 0 | 1 | 0.00 | |||
| alert_handler_entropy | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sig_int_fail | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 28.250s | 4757.260us | 1 | 1 | 100.00 | |
| clk_skew | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 29.930s | 773.673us | 1 | 1 | 100.00 | |
| random_alerts | 1 | 1 | 100.00 | |||
| alert_handler_random_alerts | 5.760s | 164.612us | 1 | 1 | 100.00 | |
| random_classes | 1 | 1 | 100.00 | |||
| alert_handler_random_classes | 50.670s | 2326.542us | 1 | 1 | 100.00 | |
| ping_timeout | 0 | 1 | 0.00 | |||
| alert_handler_ping_timeout | 14.710s | 453.007us | 0 | 1 | 0.00 | |
| lpg | 0 | 2 | 0.00 | |||
| alert_handler_lpg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_handler_lpg_stub_clk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| alert_handler_stress_all | 824.440s | 55873.499us | 1 | 1 | 100.00 | |
| alert_handler_entropy_stress_test | 1 | 1 | 100.00 | |||
| alert_handler_entropy_stress | 10.710s | 166.216us | 1 | 1 | 100.00 | |
| alert_handler_alert_accum_saturation | 1 | 1 | 100.00 | |||
| alert_handler_alert_accum_saturation | 3.430s | 29.553us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| alert_handler_intr_test | 1.790s | 8.559us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| alert_handler_tl_errors | 9.040s | 827.030us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| alert_handler_tl_errors | 9.040s | 827.030us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| alert_handler_csr_hw_reset | 3.330s | 79.884us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 7.820s | 246.741us | 1 | 1 | 100.00 | |
| alert_handler_csr_aliasing | 200.920s | 14879.940us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 21.520s | 622.754us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| alert_handler_csr_hw_reset | 3.330s | 79.884us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 7.820s | 246.741us | 1 | 1 | 100.00 | |
| alert_handler_csr_aliasing | 200.920s | 14879.940us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 21.520s | 622.754us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 124.130s | 2461.780us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 124.130s | 2461.780us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 124.130s | 2461.780us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 124.130s | 2461.780us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 255.480s | 2635.098us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| alert_handler_tl_intg_err | 2.390s | 63.004us | 1 | 1 | 100.00 | |
| alert_handler_sec_cm | 22.940s | 641.100us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| alert_handler_tl_intg_err | 2.390s | 63.004us | 1 | 1 | 100.00 | |
| sec_cm_config_shadow | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 124.130s | 2461.780us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 29.930s | 773.673us | 1 | 1 | 100.00 | |
| sec_cm_alert_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 29.930s | 773.673us | 1 | 1 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 29.930s | 773.673us | 1 | 1 | 100.00 | |
| sec_cm_class_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 29.930s | 773.673us | 1 | 1 | 100.00 | |
| sec_cm_alert_intersig_diff | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 28.250s | 4757.260us | 1 | 1 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 0 | 1 | 0.00 | |||
| alert_handler_lpg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_esc_intersig_diff | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 28.250s | 4757.260us | 1 | 1 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 0 | 1 | 0.00 | |||
| alert_handler_entropy | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 0 | 1 | 0.00 | |||
| alert_handler_entropy | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_esc_timer_fsm_sparse | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 22.940s | 641.100us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 22.940s | 641.100us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 22.940s | 641.100us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 22.940s | 641.100us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 22.940s | 641.100us | 1 | 1 | 100.00 | |
| sec_cm_accu_ctr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 22.940s | 641.100us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 22.940s | 641.100us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 22.940s | 641.100us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 22.940s | 641.100us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| alert_handler_stress_all_with_rand_reset | 41.510s | 796.008us | 0 | 1 | 0.00 | |