| chip_sw_spi_device_flash_mode |
0 |
1 |
0.00 |
|
chip_sw_uart_tx_rx_bootstrap |
110.410s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_spi_device_pass_through |
0 |
1 |
0.00 |
|
chip_sw_spi_device_pass_through |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_spi_device_pass_through_collision |
0 |
1 |
0.00 |
|
chip_sw_spi_device_pass_through_collision |
317.710s |
289.589us |
0 |
1 |
0.00
|
| chip_sw_spi_device_tpm |
0 |
1 |
0.00 |
|
chip_sw_spi_device_tpm |
58.409s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_spi_host_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_spi_host_tx_rx |
40.960s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_i2c_host_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_i2c_host_tx_rx |
74.894s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_i2c_device_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_i2c_device_tx_rx |
91.592s |
0.000us |
0 |
1 |
0.00
|
| chip_pin_mux |
0 |
1 |
0.00 |
|
chip_padctrl_attributes |
2.520s |
0.000us |
0 |
1 |
0.00
|
| chip_padctrl_attributes |
0 |
1 |
0.00 |
|
chip_padctrl_attributes |
2.520s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sleep_pin_wake |
0 |
1 |
0.00 |
|
chip_sw_sleep_pin_wake |
132.164s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sleep_pin_retention |
0 |
1 |
0.00 |
|
chip_sw_sleep_pin_retention |
113.077s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_data_integrity |
0 |
1 |
0.00 |
|
chip_sw_data_integrity_escalation |
125.543s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_instruction_integrity |
0 |
1 |
0.00 |
|
chip_sw_data_integrity_escalation |
125.543s |
0.000us |
0 |
1 |
0.00
|
| chip_jtag_csr_rw |
0 |
1 |
0.00 |
|
chip_jtag_csr_rw |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_jtag_mem_access |
0 |
1 |
0.00 |
|
chip_jtag_mem_access |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_rv_dm_ndm_reset_req |
0 |
1 |
0.00 |
|
chip_rv_dm_ndm_reset_req |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted |
0 |
1 |
0.00 |
|
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted |
8.287s |
0.000us |
0 |
1 |
0.00
|
| chip_rv_dm_access_after_wakeup |
0 |
1 |
0.00 |
|
chip_sw_rv_dm_access_after_wakeup |
8.190s |
0.000us |
0 |
1 |
0.00
|
| chip_rv_dm_lc_disabled |
0 |
1 |
0.00 |
|
chip_rv_dm_lc_disabled |
167.770s |
251.412us |
0 |
1 |
0.00
|
| chip_sw_timer |
1 |
1 |
100.00 |
|
chip_sw_rv_timer_irq |
248.260s |
248.744us |
1 |
1 |
100.00
|
| chip_sw_aon_timer_wakeup_irq |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_irq |
388.660s |
523.549us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_wdog_bark_irq |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_irq |
388.660s |
523.549us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_wdog_lc_escalate |
1 |
1 |
100.00 |
|
chip_sw_aon_timer_wdog_lc_escalate |
350.270s |
348.474us |
1 |
1 |
100.00
|
| chip_sw_aon_timer_wdog_bite_reset |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
208.750s |
164.305us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_sleep_wdog_bite_reset |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
208.750s |
164.305us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_sleep_wdog_sleep_pause |
1 |
1 |
100.00 |
|
chip_sw_aon_timer_sleep_wdog_sleep_pause |
310.920s |
2271.418us |
1 |
1 |
100.00
|
| chip_sw_plic_sw_irq |
0 |
1 |
0.00 |
|
chip_sw_plic_sw_irq |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_idle_trans |
2 |
4 |
50.00 |
|
chip_sw_otbn_randomness |
282.710s |
225.727us |
1 |
1 |
100.00
|
|
chip_sw_aes_idle |
159.040s |
147.304us |
1 |
1 |
100.00
|
|
chip_sw_hmac_enc_idle |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_kmac_idle |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_off_trans |
0 |
4 |
0.00 |
|
chip_sw_clkmgr_off_aes_trans |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_hmac_trans |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_kmac_trans |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_otbn_trans |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_jitter |
0 |
7 |
0.00 |
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
38.950s |
10.200us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en |
36.450s |
10.300us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
32.000s |
10.400us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
8.438s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_jitter |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_extended_range |
0 |
8 |
0.00 |
|
chip_sw_clkmgr_jitter_reduced_freq |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq |
32.230s |
10.260us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en_reduced_freq |
32.570s |
10.140us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en_reduced_freq |
31.990s |
10.200us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq |
32.320s |
10.240us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq |
31.880s |
10.120us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq |
31.420s |
10.400us |
0 |
1 |
0.00
|
|
chip_sw_csrng_edn_concurrency_reduced_freq |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_deep_sleep_frequency |
0 |
1 |
0.00 |
|
chip_sw_ast_clk_outputs |
8.604s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_sleep_frequency |
0 |
1 |
0.00 |
|
chip_sw_clkmgr_sleep_frequency |
9.361s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_reset_frequency |
0 |
1 |
0.00 |
|
chip_sw_clkmgr_reset_frequency |
10.140s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_external_full_reset |
1 |
1 |
100.00 |
|
chip_sw_pwrmgr_full_aon_reset |
321.940s |
504.957us |
1 |
1 |
100.00
|
| chip_sw_pwrmgr_sleep_all_reset_reqs |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
208.750s |
164.305us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_wdog_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_wdog_reset |
9.397s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_aon_power_glitch_reset |
1 |
1 |
100.00 |
|
chip_sw_pwrmgr_full_aon_reset |
321.940s |
504.957us |
1 |
1 |
100.00
|
| chip_sw_pwrmgr_main_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_main_power_glitch_reset |
11.806s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_random_sleep_power_glitch_reset |
16.300s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_deep_sleep_power_glitch_reset |
20.808s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_sleep_power_glitch_reset |
11.681s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_sleep_disabled |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_sleep_disabled |
17.566s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sys_reset_info |
0 |
1 |
0.00 |
|
chip_rv_dm_ndm_reset_req |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_cpu_info |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
332.000s |
375.248us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sw_req_reset |
1 |
1 |
100.00 |
|
chip_sw_rstmgr_sw_req |
252.640s |
267.345us |
1 |
1 |
100.00
|
| chip_sw_rstmgr_alert_info |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_alert_info |
316.100s |
289.793us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sw_rst |
1 |
1 |
100.00 |
|
chip_sw_rstmgr_sw_rst |
168.540s |
144.131us |
1 |
1 |
100.00
|
| chip_sw_rstmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_alerts |
0 |
1 |
0.00 |
|
chip_sw_alert_test |
13.818s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_escalations |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_escalation |
11.560s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_all_escalation_resets |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_entropy |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_entropy |
9.852s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_crashdump |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_alert_info |
316.100s |
289.793us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_ping_timeout |
1 |
1 |
100.00 |
|
chip_sw_alert_handler_ping_timeout |
243.610s |
313.459us |
1 |
1 |
100.00
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_sleep_mode_alerts |
10.399s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_sleep_mode_pings |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_sleep_mode_pings |
11.884s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_clock_off |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_clkoff |
10.655s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_reset_toggle |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_reset_toggle |
10.267s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_reverse_ping_in_deep_sleep |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_reverse_ping_in_deep_sleep |
10.042s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_alert_handler_escalation |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_escalation |
11.560s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_jtag_access |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
25.479s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_otp_hw_cfg |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_otp_hw_cfg |
11.905s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_init |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
25.479s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_transitions |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
25.479s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_kmac_req |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
25.479s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_key_div |
0 |
1 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation_prod |
192.630s |
267.943us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_broadcast |
1 |
10 |
10.00 |
|
chip_prim_tl_access |
155.790s |
260.006us |
1 |
1 |
100.00
|
|
chip_rv_dm_lc_disabled |
167.770s |
251.412us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_test_unlocked0 |
36.821s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_dev |
24.312s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_prod |
10.048s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_rma |
23.810s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_ctrl_transition |
25.479s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation |
201.290s |
268.123us |
0 |
1 |
0.00
|
|
chip_sw_rom_ctrl_integrity_check |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_execution_main |
8.332s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_aes_enc |
1 |
2 |
50.00 |
|
chip_sw_aes_enc |
171.200s |
157.116us |
1 |
1 |
100.00
|
|
chip_sw_aes_enc_jitter_en |
36.450s |
10.300us |
0 |
1 |
0.00
|
| chip_sw_aes_entropy |
1 |
1 |
100.00 |
|
chip_sw_aes_entropy |
147.920s |
145.822us |
1 |
1 |
100.00
|
| chip_sw_aes_idle |
1 |
1 |
100.00 |
|
chip_sw_aes_idle |
159.040s |
147.304us |
1 |
1 |
100.00
|
| chip_sw_hmac_enc |
1 |
2 |
50.00 |
|
chip_sw_hmac_enc |
150.720s |
156.381us |
1 |
1 |
100.00
|
|
chip_sw_hmac_enc_jitter_en |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_hmac_idle |
0 |
1 |
0.00 |
|
chip_sw_hmac_enc_idle |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_kmac_enc |
0 |
3 |
0.00 |
|
chip_sw_kmac_mode_cshake |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_keymgr |
0 |
1 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation |
201.290s |
268.123us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_lc |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
25.479s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_rom |
0 |
1 |
0.00 |
|
chip_sw_kmac_app_rom |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_kmac_entropy |
1 |
1 |
100.00 |
|
chip_sw_kmac_entropy |
244.130s |
203.311us |
1 |
1 |
100.00
|
| chip_sw_kmac_idle |
0 |
1 |
0.00 |
|
chip_sw_kmac_idle |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_entropy_src_csrng |
1 |
1 |
100.00 |
|
chip_sw_entropy_src_csrng |
277.780s |
260.764us |
1 |
1 |
100.00
|
| chip_sw_csrng_edn_cmd |
1 |
1 |
100.00 |
|
chip_sw_entropy_src_csrng |
277.780s |
260.764us |
1 |
1 |
100.00
|
| chip_sw_csrng_fuse_en_sw_app_read |
0 |
1 |
0.00 |
|
chip_sw_csrng_fuse_en_sw_app_read_test |
11.543s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_csrng_known_answer_tests |
1 |
1 |
100.00 |
|
chip_sw_csrng_kat_test |
162.830s |
156.787us |
1 |
1 |
100.00
|
| chip_sw_edn_entropy_reqs |
1 |
1 |
100.00 |
|
chip_sw_csrng_edn_concurrency |
718.390s |
678.550us |
1 |
1 |
100.00
|
| chip_sw_keymgr_dpe_key_derivation |
0 |
2 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation |
201.290s |
268.123us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
32.000s |
10.400us |
0 |
1 |
0.00
|
| chip_sw_otbn_op |
1 |
2 |
50.00 |
|
chip_sw_otbn_ecdsa_op_irq |
2154.120s |
1472.468us |
1 |
1 |
100.00
|
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
38.950s |
10.200us |
0 |
1 |
0.00
|
| chip_sw_otbn_rnd_entropy |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
282.710s |
225.727us |
1 |
1 |
100.00
|
| chip_sw_otbn_urnd_entropy |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
282.710s |
225.727us |
1 |
1 |
100.00
|
| chip_sw_otbn_idle |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
282.710s |
225.727us |
1 |
1 |
100.00
|
| chip_sw_otbn_mem_scramble |
1 |
1 |
100.00 |
|
chip_sw_otbn_mem_scramble |
340.890s |
264.823us |
1 |
1 |
100.00
|
| chip_sw_rom_access |
0 |
1 |
0.00 |
|
chip_sw_rom_ctrl_integrity_check |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_rom_ctrl_integrity_check |
0 |
1 |
0.00 |
|
chip_sw_rom_ctrl_integrity_check |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sram_scrambled_access |
0 |
2 |
0.00 |
|
chip_sw_sram_ctrl_scrambled_access |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
8.438s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sram_execution |
0 |
1 |
0.00 |
|
chip_sw_sram_ctrl_execution_main |
8.332s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sram_lc_escalation |
0 |
2 |
0.00 |
|
chip_sw_all_escalation_resets |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_data_integrity_escalation |
125.543s |
0.000us |
0 |
1 |
0.00
|
| chip_otp_ctrl_init |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
25.479s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_keys |
1 |
4 |
25.00 |
|
chip_sw_otbn_mem_scramble |
340.890s |
264.823us |
1 |
1 |
100.00
|
|
chip_sw_keymgr_dpe_key_derivation |
201.290s |
268.123us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_rv_core_ibex_icache_invalidate |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_entropy |
1 |
4 |
25.00 |
|
chip_sw_otbn_mem_scramble |
340.890s |
264.823us |
1 |
1 |
100.00
|
|
chip_sw_keymgr_dpe_key_derivation |
201.290s |
268.123us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_rv_core_ibex_icache_invalidate |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_program |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
25.479s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_program_error |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_program_error |
8.514s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_hw_cfg |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_otp_hw_cfg |
11.905s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_lc_signals |
1 |
6 |
16.67 |
|
chip_prim_tl_access |
155.790s |
260.006us |
1 |
1 |
100.00
|
|
chip_sw_otp_ctrl_lc_signals_test_unlocked0 |
36.821s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_dev |
24.312s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_prod |
10.048s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_rma |
23.810s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_ctrl_transition |
25.479s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_prim_tl_access |
1 |
1 |
100.00 |
|
chip_prim_tl_access |
155.790s |
260.006us |
1 |
1 |
100.00
|
| chip_sw_otp_ctrl_nvm_cnt |
0 |
1 |
0.00 |
|
chip_sw_otp_ctrl_nvm_cnt |
27.381s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_sw_parts |
0 |
1 |
0.00 |
|
chip_sw_otp_ctrl_sw_parts |
30.259s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_ast_clk_outputs |
0 |
1 |
0.00 |
|
chip_sw_ast_clk_outputs |
8.604s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_ast_sys_clk_jitter |
0 |
7 |
0.00 |
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
38.950s |
10.200us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en |
36.450s |
10.300us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
32.000s |
10.400us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
8.438s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_jitter |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_external_reset_requests |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_smoketest |
146.050s |
143.520us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_external_irqs |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_smoketest |
146.050s |
143.520us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_external_wakeup_requests |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_external_wakeup |
159.920s |
138.788us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_gpios |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_gpios |
147.870s |
136.497us |
0 |
1 |
0.00
|
| chip_sw_nmi_irq |
0 |
1 |
0.00 |
|
chip_sw_rv_core_ibex_nmi_irq |
286.930s |
251.614us |
0 |
1 |
0.00
|
| chip_sw_rv_core_ibex_rnd |
1 |
1 |
100.00 |
|
chip_sw_rv_core_ibex_rnd |
224.120s |
198.635us |
1 |
1 |
100.00
|
| chip_sw_rv_core_ibex_address_translation |
0 |
1 |
0.00 |
|
chip_sw_rv_core_ibex_address_translation |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_rv_core_ibex_icache_scrambled_access |
0 |
1 |
0.00 |
|
chip_sw_rv_core_ibex_icache_invalidate |
0.000s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_rv_core_ibex_fault_dump |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
332.000s |
375.248us |
0 |
1 |
0.00
|
| chip_sw_rv_core_ibex_double_fault |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
332.000s |
375.248us |
0 |
1 |
0.00
|
| chip_sw_smoketest |
11 |
14 |
78.57 |
|
chip_sw_aes_smoketest |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_aon_timer_smoketest |
138.350s |
163.255us |
1 |
1 |
100.00
|
|
chip_sw_clkmgr_smoketest |
116.220s |
142.978us |
1 |
1 |
100.00
|
|
chip_sw_csrng_smoketest |
118.650s |
144.845us |
1 |
1 |
100.00
|
|
chip_sw_gpio_smoketest |
139.550s |
174.213us |
1 |
1 |
100.00
|
|
chip_sw_hmac_smoketest |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_kmac_smoketest |
144.580s |
171.102us |
1 |
1 |
100.00
|
|
chip_sw_otbn_smoketest |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_smoketest |
121.620s |
148.072us |
1 |
1 |
100.00
|
|
chip_sw_rv_plic_smoketest |
120.000s |
145.039us |
1 |
1 |
100.00
|
|
chip_sw_rv_timer_smoketest |
176.320s |
248.735us |
1 |
1 |
100.00
|
|
chip_sw_rstmgr_smoketest |
119.320s |
141.630us |
1 |
1 |
100.00
|
|
chip_sw_sram_ctrl_smoketest |
120.850s |
145.463us |
1 |
1 |
100.00
|
|
chip_sw_uart_smoketest |
127.330s |
155.649us |
1 |
1 |
100.00
|
| chip_sw_rom_functests |
0 |
1 |
0.00 |
|
rom_keymgr_functest |
8.158s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_signed |
0 |
1 |
0.00 |
|
chip_sw_uart_smoketest_signed |
8.211s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_boot |
0 |
1 |
0.00 |
|
chip_sw_uart_tx_rx_bootstrap |
110.410s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_secure_boot |
0 |
1 |
0.00 |
|
base_rom_e2e_smoke |
8.648s |
0.000us |
0 |
1 |
0.00
|
| chip_lc_scrap |
4 |
4 |
100.00 |
|
chip_sw_lc_ctrl_rma_to_scrap |
188.280s |
215.341us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_raw_to_scrap |
187.920s |
221.822us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_test_locked0_to_scrap |
164.800s |
218.592us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_rand_to_scrap |
208.570s |
218.002us |
1 |
1 |
100.00
|
| chip_lc_test_locked |
0 |
2 |
0.00 |
|
chip_rv_dm_lc_disabled |
167.770s |
251.412us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_testunlocks |
30.522s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_walkthrough |
0 |
5 |
0.00 |
|
chip_sw_lc_walkthrough_dev |
14.152s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_prod |
21.252s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_prodend |
13.332s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_rma |
29.996s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_testunlocks |
30.522s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_volatile_raw_unlock |
2 |
3 |
66.67 |
|
chip_sw_lc_ctrl_volatile_raw_unlock |
423.820s |
536.412us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz |
380.810s |
513.248us |
1 |
1 |
100.00
|
|
rom_volatile_raw_unlock |
8.173s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_rom_raw_unlock |
0 |
1 |
0.00 |
|
rom_raw_unlock |
8.172s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_exit_test_unlocked_bootstrap |
0 |
1 |
0.00 |
|
chip_sw_exit_test_unlocked_bootstrap |
90.782s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_inject_scramble_seed |
0 |
1 |
0.00 |
|
chip_sw_inject_scramble_seed |
109.056s |
0.000us |
0 |
1 |
0.00
|
| tl_d_oob_addr_access |
0 |
1 |
0.00 |
|
chip_tl_errors |
94.970s |
117.711us |
0 |
1 |
0.00
|
| tl_d_illegal_access |
0 |
1 |
0.00 |
|
chip_tl_errors |
94.970s |
117.711us |
0 |
1 |
0.00
|
| tl_d_outstanding_access |
0 |
2 |
0.00 |
|
chip_csr_aliasing |
8.930s |
0.000us |
0 |
1 |
0.00
|
|
chip_same_csr_outstanding |
13.620s |
0.000us |
0 |
1 |
0.00
|
| tl_d_partial_access |
0 |
2 |
0.00 |
|
chip_csr_aliasing |
8.930s |
0.000us |
0 |
1 |
0.00
|
|
chip_same_csr_outstanding |
13.620s |
0.000us |
0 |
1 |
0.00
|
| xbar_base_random_sequence |
1 |
1 |
100.00 |
|
xbar_random |
51.320s |
37.245us |
1 |
1 |
100.00
|
| xbar_random_delay |
4 |
6 |
66.67 |
|
xbar_smoke_zero_delays |
8.830s |
13.346us |
1 |
1 |
100.00
|
|
xbar_smoke_large_delays |
232.300s |
1887.012us |
1 |
1 |
100.00
|
|
xbar_smoke_slow_rsp |
356.240s |
2027.015us |
1 |
1 |
100.00
|
|
xbar_random_zero_delays |
78.520s |
60.453us |
1 |
1 |
100.00
|
|
xbar_random_large_delays |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
xbar_random_slow_rsp |
0.000s |
0.000us |
0 |
1 |
0.00
|
| xbar_unmapped_address |
2 |
2 |
100.00 |
|
xbar_unmapped_addr |
42.300s |
66.701us |
1 |
1 |
100.00
|
|
xbar_error_and_unmapped_addr |
43.570s |
30.503us |
1 |
1 |
100.00
|
| xbar_error_cases |
2 |
2 |
100.00 |
|
xbar_error_random |
134.930s |
371.717us |
1 |
1 |
100.00
|
|
xbar_error_and_unmapped_addr |
43.570s |
30.503us |
1 |
1 |
100.00
|
| xbar_all_access_same_device |
2 |
2 |
100.00 |
|
xbar_access_same_device |
13.380s |
8.874us |
1 |
1 |
100.00
|
|
xbar_access_same_device_slow_rsp |
409.710s |
2264.846us |
1 |
1 |
100.00
|
| xbar_all_hosts_use_same_source_id |
1 |
1 |
100.00 |
|
xbar_same_source |
62.360s |
151.437us |
1 |
1 |
100.00
|
| xbar_stress_all |
1 |
2 |
50.00 |
|
xbar_stress_all |
58.390s |
42.013us |
1 |
1 |
100.00
|
|
xbar_stress_all_with_error |
0.000s |
0.000us |
0 |
1 |
0.00
|
| xbar_stress_with_reset |
0 |
2 |
0.00 |
|
xbar_stress_all_with_rand_reset |
0.000s |
0.000us |
0 |
1 |
0.00
|
|
xbar_stress_all_with_reset_error |
0.000s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_smoke |
0 |
1 |
0.00 |
|
rom_e2e_smoke |
8.238s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_shutdown_output |
0 |
1 |
0.00 |
|
rom_e2e_shutdown_output |
8.192s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_shutdown_exception_c |
0 |
1 |
0.00 |
|
rom_e2e_shutdown_exception_c |
8.148s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_boot_policy_valid |
0 |
15 |
0.00 |
|
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 |
8.100s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_dev |
8.303s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_prod |
8.149s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_prod_end |
8.192s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_rma |
8.403s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 |
8.189s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_dev |
8.290s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_prod |
8.169s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end |
8.208s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_rma |
8.204s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 |
35.899s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_dev |
28.874s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_prod |
34.691s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end |
34.438s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_rma |
34.740s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_sigverify_always |
0 |
15 |
0.00 |
|
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 |
35.193s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_dev |
35.069s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_prod |
35.332s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_prod_end |
35.087s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_rma |
34.580s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 |
34.694s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_dev |
34.486s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_prod |
34.775s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end |
34.782s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_rma |
33.077s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 |
8.909s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_dev |
21.456s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_prod |
8.498s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end |
8.401s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_rma |
8.306s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_asm_init |
0 |
5 |
0.00 |
|
rom_e2e_asm_init_test_unlocked0 |
8.204s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_dev |
8.154s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_prod |
8.607s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_prod_end |
8.152s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_rma |
8.205s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_keymgr_init |
0 |
3 |
0.00 |
|
rom_e2e_keymgr_init_rom_ext_meas |
8.205s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_keymgr_init_rom_ext_no_meas |
8.198s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_keymgr_init_rom_ext_invalid_meas |
8.174s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_static_critical |
0 |
1 |
0.00 |
|
rom_e2e_static_critical |
8.304s |
0.000us |
0 |
1 |
0.00
|