Simulation Results: clkmgr

 
24/11/2025 16:08:31 sha: e65c354 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 71.49
  • line
  • 81.74
  • cond
  • 78.11
  • toggle
  • 94.81
  • fsm
  • 0.0
  • branch
  • 86.59
  • assert
  • 89.26
  • group
  • 69.92
Validation stages
V1
75.00%
V2
68.42%
V2S
52.94%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.850s 157.764us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.950s 45.875us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.740s 18.280us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 4.870s 483.560us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.780s 15.993us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.220s 78.801us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.740s 18.280us 1 1 100.00
clkmgr_csr_aliasing 0.780s 15.993us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.910s 46.573us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.890s 46.937us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.710s 16.069us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.850s 157.764us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.710s 9.310us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.560s 3.084us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.710s 9.310us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.810s 134.050us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.930s 44.438us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.280s 130.583us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.280s 130.583us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
clkmgr_csr_hw_reset 0.950s 45.875us 1 1 100.00
clkmgr_csr_rw 0.740s 18.280us 1 1 100.00
clkmgr_csr_aliasing 0.780s 15.993us 1 1 100.00
clkmgr_same_csr_outstanding 0.630s 2.506us 0 1 0.00
tl_d_partial_access 3 4 75.00
clkmgr_csr_hw_reset 0.950s 45.875us 1 1 100.00
clkmgr_csr_rw 0.740s 18.280us 1 1 100.00
clkmgr_csr_aliasing 0.780s 15.993us 1 1 100.00
clkmgr_same_csr_outstanding 0.630s 2.506us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 1.900s 129.710us 0 1 0.00
clkmgr_tl_intg_err 0.970s 47.843us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.300s 80.124us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.300s 80.124us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.300s 80.124us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.300s 80.124us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.670s 5.190us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.970s 47.843us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.710s 9.310us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.560s 3.084us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.300s 80.124us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.070s 58.095us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.740s 18.280us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.900s 129.710us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.740s 18.280us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.740s 18.280us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.900s 129.710us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.720s 3.178us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.410s 54.689us 0 1 0.00