Simulation Results: dma

 
24/11/2025 16:08:31 sha: e65c354 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • score
  • 89.72
  • block
  • 97.38
  • branch
  • 95.83
  • statement
  • 96.89
  • expression
  • 94.11
  • toggle
  • 83.12
  • fsm
  • 92.96
  • assertion
  • 95.66
  • covergroup
  • 66.0
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 4983.061us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 1688.004us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 308.931us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 50.002us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 18.606us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 6.000s 2087.965us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 4.000s 224.490us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 24.764us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 18.606us 1 1 100.00
dma_csr_aliasing 4.000s 224.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 94.000s 4969.664us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 196.000s 109247.194us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 444.000s 71347.809us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 444.000s 71347.809us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 196.000s 109247.194us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 246.000s 62302.968us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 444.000s 71347.809us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 10.000s 957.181us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 344.000s 31789.759us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 19.087us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 19.497us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 47.668us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 47.668us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 50.002us 1 1 100.00
dma_csr_rw 1.000s 18.606us 1 1 100.00
dma_csr_aliasing 4.000s 224.490us 1 1 100.00
dma_same_csr_outstanding 1.000s 186.466us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 50.002us 1 1 100.00
dma_csr_rw 1.000s 18.606us 1 1 100.00
dma_csr_aliasing 4.000s 224.490us 1 1 100.00
dma_same_csr_outstanding 1.000s 186.466us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 15.000s 283.156us 1 1 100.00
dma_generic_stress 246.000s 62302.968us 1 1 100.00
dma_handshake_stress 444.000s 71347.809us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 1433.600us 1 1 100.00
tl_intg_err 2 2 100.00
dma_sec_cm 2.000s 19.153us 1 1 100.00
dma_tl_intg_err 3.000s 273.760us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 98.000s 5700.096us 1 1 100.00
dma_longer_transfer 3.000s 351.697us 1 1 100.00
dma_stress_all_with_rand_reset 8.000s 916.148us 0 1 0.00