Simulation Results: edn

 
24/11/2025 16:08:31 sha: e65c354 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 84.23
  • line
  • 98.02
  • cond
  • 86.12
  • toggle
  • 84.73
  • fsm
  • 54.65
  • branch
  • 93.4
  • assert
  • 96.89
  • group
  • 75.76
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.890s 36.557us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.830s 26.632us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 26.988us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.240s 258.057us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.240s 216.873us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.940s 68.751us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 26.988us 1 1 100.00
edn_csr_aliasing 1.240s 216.873us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.160s 97.509us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.160s 97.509us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.160s 97.509us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.830s 41.654us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.920s 68.508us 1 1 100.00
errs 1 1 100.00
edn_err 0.780s 21.775us 1 1 100.00
disable 2 2 100.00
edn_disable 0.860s 41.201us 1 1 100.00
edn_disable_auto_req_mode 0.950s 49.276us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.250s 506.942us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.740s 46.298us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.830s 177.254us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.470s 156.961us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.470s 156.961us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.830s 26.632us 1 1 100.00
edn_csr_rw 0.770s 26.988us 1 1 100.00
edn_csr_aliasing 1.240s 216.873us 1 1 100.00
edn_same_csr_outstanding 0.810s 37.877us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.830s 26.632us 1 1 100.00
edn_csr_rw 0.770s 26.988us 1 1 100.00
edn_csr_aliasing 1.240s 216.873us 1 1 100.00
edn_same_csr_outstanding 0.810s 37.877us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.490s 514.362us 1 1 100.00
edn_tl_intg_err 1.320s 53.242us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.820s 18.129us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.920s 68.508us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.490s 514.362us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.490s 514.362us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.490s 514.362us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.490s 514.362us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.920s 68.508us 1 1 100.00
edn_sec_cm 3.490s 514.362us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.920s 68.508us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.320s 53.242us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00