Simulation Results: hmac

 
24/11/2025 16:08:31 sha: e65c354 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 90.06
  • line
  • 99.79
  • cond
  • 96.4
  • toggle
  • 100.0
  • fsm
  • 94.12
  • branch
  • 99.67
  • assert
  • 96.42
  • group
  • 44.02
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 1.200s 413.412us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.740s 170.788us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.830s 63.061us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 9.350s 323.460us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.570s 212.509us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.460s 148.094us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.830s 63.061us 1 1 100.00
hmac_csr_aliasing 3.570s 212.509us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 12.470s 3917.106us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 24.330s 3215.865us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 7.460s 663.350us 1 1 100.00
hmac_test_sha384_vectors 18.360s 1197.893us 1 1 100.00
hmac_test_sha512_vectors 18.260s 236.890us 1 1 100.00
hmac_test_hmac256_vectors 7.200s 762.995us 1 1 100.00
hmac_test_hmac384_vectors 7.990s 2992.790us 1 1 100.00
hmac_test_hmac512_vectors 10.480s 354.648us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 8.270s 883.726us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 308.620s 2786.629us 1 1 100.00
error 1 1 100.00
hmac_error 42.360s 15240.099us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 32.860s 16609.246us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 1.200s 413.412us 1 1 100.00
hmac_long_msg 12.470s 3917.106us 1 1 100.00
hmac_back_pressure 24.330s 3215.865us 1 1 100.00
hmac_datapath_stress 308.620s 2786.629us 1 1 100.00
hmac_burst_wr 8.270s 883.726us 1 1 100.00
hmac_stress_all 96.050s 169817.360us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 1.200s 413.412us 1 1 100.00
hmac_long_msg 12.470s 3917.106us 1 1 100.00
hmac_back_pressure 24.330s 3215.865us 1 1 100.00
hmac_datapath_stress 308.620s 2786.629us 1 1 100.00
hmac_wipe_secret 32.860s 16609.246us 1 1 100.00
hmac_test_sha256_vectors 7.460s 663.350us 1 1 100.00
hmac_test_sha384_vectors 18.360s 1197.893us 1 1 100.00
hmac_test_sha512_vectors 18.260s 236.890us 1 1 100.00
hmac_test_hmac256_vectors 7.200s 762.995us 1 1 100.00
hmac_test_hmac384_vectors 7.990s 2992.790us 1 1 100.00
hmac_test_hmac512_vectors 10.480s 354.648us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 1.200s 413.412us 1 1 100.00
hmac_long_msg 12.470s 3917.106us 1 1 100.00
hmac_back_pressure 24.330s 3215.865us 1 1 100.00
hmac_datapath_stress 308.620s 2786.629us 1 1 100.00
hmac_burst_wr 8.270s 883.726us 1 1 100.00
hmac_error 42.360s 15240.099us 1 1 100.00
hmac_wipe_secret 32.860s 16609.246us 1 1 100.00
hmac_test_sha256_vectors 7.460s 663.350us 1 1 100.00
hmac_test_sha384_vectors 18.360s 1197.893us 1 1 100.00
hmac_test_sha512_vectors 18.260s 236.890us 1 1 100.00
hmac_test_hmac256_vectors 7.200s 762.995us 1 1 100.00
hmac_test_hmac384_vectors 7.990s 2992.790us 1 1 100.00
hmac_test_hmac512_vectors 10.480s 354.648us 1 1 100.00
hmac_stress_all 96.050s 169817.360us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 96.050s 169817.360us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.560s 22.912us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.560s 44.557us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.180s 118.006us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.180s 118.006us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.740s 170.788us 1 1 100.00
hmac_csr_rw 0.830s 63.061us 1 1 100.00
hmac_csr_aliasing 3.570s 212.509us 1 1 100.00
hmac_same_csr_outstanding 1.350s 526.024us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.740s 170.788us 1 1 100.00
hmac_csr_rw 0.830s 63.061us 1 1 100.00
hmac_csr_aliasing 3.570s 212.509us 1 1 100.00
hmac_same_csr_outstanding 1.350s 526.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.730s 360.811us 1 1 100.00
hmac_tl_intg_err 3.030s 837.746us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.030s 837.746us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 1.200s 413.412us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 0.740s 21.883us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 215.250s 5484.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.780s 33.649us 1 1 100.00