| V1 |
|
100.00% |
| V2 |
|
85.00% |
| V2S |
|
64.29% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| lc_ctrl_smoke | 1.450s | 23.781us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_hw_reset | 0.960s | 131.502us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_rw | 0.800s | 17.997us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_bit_bash | 2.480s | 334.700us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_aliasing | 1.210s | 92.702us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_mem_rw_with_rand_reset | 1.250s | 190.539us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| lc_ctrl_csr_rw | 0.800s | 17.997us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 1.210s | 92.702us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| state_post_trans | 0 | 1 | 0.00 | |||
| lc_ctrl_state_post_trans | 4.940s | 59.368us | 0 | 1 | 0.00 | |
| regwen_during_op | 1 | 1 | 100.00 | |||
| lc_ctrl_regwen_during_op | 9.540s | 987.464us | 1 | 1 | 100.00 | |
| rand_wr_claim_transition_if | 1 | 1 | 100.00 | |||
| lc_ctrl_claim_transition_if | 0.790s | 22.541us | 1 | 1 | 100.00 | |
| lc_prog_failure | 1 | 1 | 100.00 | |||
| lc_ctrl_prog_failure | 1.270s | 91.006us | 1 | 1 | 100.00 | |
| lc_state_failure | 0 | 1 | 0.00 | |||
| lc_ctrl_state_failure | 4.890s | 20.945us | 0 | 1 | 0.00 | |
| lc_errors | 1 | 1 | 100.00 | |||
| lc_ctrl_errors | 6.010s | 1260.458us | 1 | 1 | 100.00 | |
| security_escalation | 5 | 7 | 71.43 | |||
| lc_ctrl_state_failure | 4.890s | 20.945us | 0 | 1 | 0.00 | |
| lc_ctrl_prog_failure | 1.270s | 91.006us | 1 | 1 | 100.00 | |
| lc_ctrl_errors | 6.010s | 1260.458us | 1 | 1 | 100.00 | |
| lc_ctrl_security_escalation | 5.870s | 223.082us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_state_failure | 8.310s | 1571.014us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_prog_failure | 6.510s | 573.369us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_errors | 34.020s | 24360.130us | 1 | 1 | 100.00 | |
| jtag_access | 12 | 13 | 92.31 | |||
| lc_ctrl_jtag_csr_hw_reset | 1.680s | 109.508us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_rw | 1.350s | 55.510us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_bit_bash | 21.120s | 5280.275us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_aliasing | 5.220s | 566.066us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_same_csr_outstanding | 1.500s | 331.056us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 2.170s | 1278.780us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_alert_test | 1.320s | 285.960us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_smoke | 1.400s | 406.918us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_state_post_trans | 5.250s | 923.393us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_prog_failure | 6.510s | 573.369us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_errors | 34.020s | 24360.130us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_access | 4.920s | 2706.599us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_regwen_during_op | 14.360s | 5458.647us | 1 | 1 | 100.00 | |
| jtag_priority | 1 | 1 | 100.00 | |||
| lc_ctrl_jtag_priority | 3.280s | 528.614us | 1 | 1 | 100.00 | |
| lc_ctrl_volatile_unlock | 1 | 1 | 100.00 | |||
| lc_ctrl_volatile_unlock_smoke | 1.020s | 27.392us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| lc_ctrl_stress_all | 5.470s | 29.332us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| lc_ctrl_alert_test | 0.890s | 81.236us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_errors | 1.400s | 292.112us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_errors | 1.400s | 292.112us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| lc_ctrl_csr_hw_reset | 0.960s | 131.502us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_rw | 0.800s | 17.997us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 1.210s | 92.702us | 1 | 1 | 100.00 | |
| lc_ctrl_same_csr_outstanding | 1.430s | 37.161us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| lc_ctrl_csr_hw_reset | 0.960s | 131.502us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_rw | 0.800s | 17.997us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 1.210s | 92.702us | 1 | 1 | 100.00 | |
| lc_ctrl_same_csr_outstanding | 1.430s | 37.161us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| lc_ctrl_tl_intg_err | 2.230s | 354.998us | 1 | 1 | 100.00 | |
| lc_ctrl_sec_cm | 7.050s | 135.956us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_intg_err | 2.230s | 354.998us | 1 | 1 | 100.00 | |
| sec_cm_transition_config_regwen | 1 | 1 | 100.00 | |||
| lc_ctrl_regwen_during_op | 9.540s | 987.464us | 1 | 1 | 100.00 | |
| sec_cm_manuf_state_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 4.890s | 20.945us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 7.050s | 135.956us | 1 | 1 | 100.00 | |
| sec_cm_transition_ctr_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 4.890s | 20.945us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 7.050s | 135.956us | 1 | 1 | 100.00 | |
| sec_cm_manuf_state_bkgn_chk | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 4.890s | 20.945us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 7.050s | 135.956us | 1 | 1 | 100.00 | |
| sec_cm_transition_ctr_bkgn_chk | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 4.890s | 20.945us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 7.050s | 135.956us | 1 | 1 | 100.00 | |
| sec_cm_state_config_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 4.890s | 20.945us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 7.050s | 135.956us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 4.890s | 20.945us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 7.050s | 135.956us | 1 | 1 | 100.00 | |
| sec_cm_kmac_fsm_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 4.890s | 20.945us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 7.050s | 135.956us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_local_esc | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 4.890s | 20.945us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 7.050s | 135.956us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_global_esc | 1 | 1 | 100.00 | |||
| lc_ctrl_security_escalation | 5.870s | 223.082us | 1 | 1 | 100.00 | |
| sec_cm_main_ctrl_flow_consistency | 0 | 2 | 0.00 | |||
| lc_ctrl_state_post_trans | 4.940s | 59.368us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_state_post_trans | 5.250s | 923.393us | 0 | 1 | 0.00 | |
| sec_cm_intersig_mubi | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_mubi | 10.770s | 457.152us | 1 | 1 | 100.00 | |
| sec_cm_token_valid_ctrl_mubi | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_mubi | 10.770s | 457.152us | 1 | 1 | 100.00 | |
| sec_cm_token_digest | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_token_digest | 7.030s | 1056.926us | 1 | 1 | 100.00 | |
| sec_cm_token_mux_ctrl_redun | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_token_mux | 5.120s | 586.624us | 1 | 1 | 100.00 | |
| sec_cm_token_valid_mux_redun | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_token_mux | 5.120s | 586.624us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| lc_ctrl_stress_all_with_rand_reset | 29.770s | 4625.372us | 0 | 1 | 0.00 | |