| V1 |
|
100.00% |
| V2 |
|
93.75% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_smoke | 1 | 1 | 100.00 | |||
| mbx_smoke | 47.000s | 2731.061us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 19.243us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| mbx_csr_rw | 1.000s | 52.406us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| mbx_csr_bit_bash | 4.000s | 926.284us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| mbx_csr_aliasing | 2.000s | 19.205us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| mbx_csr_mem_rw_with_rand_reset | 2.000s | 32.167us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| mbx_csr_rw | 1.000s | 52.406us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 19.205us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_stress | 1 | 1 | 100.00 | |||
| mbx_stress | 66.000s | 28192.839us | 1 | 1 | 100.00 | |
| mbx_max_activity | 1 | 1 | 100.00 | |||
| mbx_stress_zero_delays | 87.000s | 4530.688us | 1 | 1 | 100.00 | |
| mbx_imbx_oob | 0 | 1 | 0.00 | |||
| mbx_imbx_oob | 17.000s | 8046.324us | 0 | 1 | 0.00 | |
| mbx_doe_intr_msg | 1 | 1 | 100.00 | |||
| mbx_doe_intr_msg | 9.000s | 2974.645us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| mbx_alert_test | 2.000s | 36.219us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| mbx_intr_test | 2.000s | 12.448us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 3.000s | 35.701us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 3.000s | 35.701us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 19.243us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 52.406us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 19.205us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 1.000s | 29.809us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 19.243us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 52.406us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 19.205us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 1.000s | 29.809us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| mbx_sec_cm | 1.000s | 13.699us | 1 | 1 | 100.00 | |
| mbx_tl_intg_err | 2.000s | 264.686us | 1 | 1 | 100.00 | |