Simulation Results: rom_ctrl

 
24/11/2025 16:08:31 sha: e65c354 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 97.48
  • line
  • 99.46
  • cond
  • 93.46
  • toggle
  • 99.59
  • fsm
  • 100.0
  • branch
  • 98.18
  • assert
  • 95.49
  • group
  • 96.18
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.510s 1908.297us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.450s 835.551us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.830s 170.788us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.270s 232.962us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.100s 371.261us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.530s 179.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.830s 170.788us 1 1 100.00
rom_ctrl_csr_aliasing 3.100s 371.261us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.150s 206.014us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.310s 138.269us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 3.670s 229.230us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 19.660s 16518.363us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.220s 382.106us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.460s 123.888us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.940s 557.498us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.940s 557.498us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.450s 835.551us 1 1 100.00
rom_ctrl_csr_rw 4.830s 170.788us 1 1 100.00
rom_ctrl_csr_aliasing 3.100s 371.261us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.920s 288.238us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.450s 835.551us 1 1 100.00
rom_ctrl_csr_rw 4.830s 170.788us 1 1 100.00
rom_ctrl_csr_aliasing 3.100s 371.261us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.920s 288.238us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.440s 1872.420us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.660s 582.629us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 192.230s 566.199us 0 1 0.00
rom_ctrl_tl_intg_err 42.440s 1142.700us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 192.230s 566.199us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 192.230s 566.199us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.440s 1872.420us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.440s 1872.420us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.440s 1872.420us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.440s 1872.420us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.440s 1872.420us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 192.230s 566.199us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 192.230s 566.199us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.510s 1908.297us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.510s 1908.297us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.510s 1908.297us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 42.440s 1142.700us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.440s 1872.420us 1 1 100.00
rom_ctrl_kmac_err_chk 6.220s 382.106us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.440s 1872.420us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.440s 1872.420us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.440s 1872.420us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.660s 582.629us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 192.230s 566.199us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 55.680s 3660.961us 1 1 100.00