Simulation Results: rom_ctrl

 
24/11/2025 16:08:31 sha: e65c354 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 96.11
  • line
  • 99.32
  • cond
  • 92.57
  • toggle
  • 99.59
  • fsm
  • 93.33
  • branch
  • 97.45
  • assert
  • 95.49
  • group
  • 94.99
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.330s 650.175us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.430s 624.868us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.910s 214.143us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.250s 1024.579us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.870s 1933.889us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.260s 409.979us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.910s 214.143us 1 1 100.00
rom_ctrl_csr_aliasing 6.870s 1933.889us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.170s 212.093us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.790s 360.588us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.700s 547.405us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 24.310s 1607.645us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.800s 546.053us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.920s 377.297us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.510s 950.593us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.510s 950.593us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.430s 624.868us 1 1 100.00
rom_ctrl_csr_rw 6.910s 214.143us 1 1 100.00
rom_ctrl_csr_aliasing 6.870s 1933.889us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.740s 360.651us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.430s 624.868us 1 1 100.00
rom_ctrl_csr_rw 6.910s 214.143us 1 1 100.00
rom_ctrl_csr_aliasing 6.870s 1933.889us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.740s 360.651us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.050s 15345.750us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 26.610s 4226.061us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 454.260s 784.566us 0 1 0.00
rom_ctrl_tl_intg_err 52.790s 439.279us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 454.260s 784.566us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 454.260s 784.566us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.050s 15345.750us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.050s 15345.750us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.050s 15345.750us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.050s 15345.750us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.050s 15345.750us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 454.260s 784.566us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 454.260s 784.566us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.330s 650.175us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.330s 650.175us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.330s 650.175us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 52.790s 439.279us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.050s 15345.750us 1 1 100.00
rom_ctrl_kmac_err_chk 14.800s 546.053us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.050s 15345.750us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.050s 15345.750us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.050s 15345.750us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 26.610s 4226.061us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 454.260s 784.566us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 81.900s 1955.164us 1 1 100.00