| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| rstmgr_smoke | 1.010s | 61.249us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rstmgr_csr_hw_reset | 0.940s | 64.007us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rstmgr_csr_rw | 0.860s | 36.733us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rstmgr_csr_bit_bash | 1.770s | 51.571us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rstmgr_csr_aliasing | 1.150s | 40.655us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| rstmgr_csr_mem_rw_with_rand_reset | 0.980s | 67.678us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rstmgr_csr_rw | 0.860s | 36.733us | 1 | 1 | 100.00 | |
| rstmgr_csr_aliasing | 1.150s | 40.655us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_stretcher | 1 | 1 | 100.00 | |||
| rstmgr_por_stretcher | 1.250s | 167.273us | 1 | 1 | 100.00 | |
| sw_rst | 1 | 1 | 100.00 | |||
| rstmgr_sw_rst | 0.910s | 44.272us | 1 | 1 | 100.00 | |
| sw_rst_reset_race | 1 | 1 | 100.00 | |||
| rstmgr_sw_rst_reset_race | 0.980s | 85.112us | 1 | 1 | 100.00 | |
| reset_info | 1 | 1 | 100.00 | |||
| rstmgr_reset | 4.220s | 584.044us | 1 | 1 | 100.00 | |
| cpu_info | 1 | 1 | 100.00 | |||
| rstmgr_reset | 4.220s | 584.044us | 1 | 1 | 100.00 | |
| alert_info | 1 | 1 | 100.00 | |||
| rstmgr_reset | 4.220s | 584.044us | 1 | 1 | 100.00 | |
| reset_info_capture | 1 | 1 | 100.00 | |||
| rstmgr_reset | 4.220s | 584.044us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| rstmgr_stress_all | 26.440s | 4016.493us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rstmgr_alert_test | 0.800s | 37.215us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| rstmgr_tl_errors | 1.810s | 47.129us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| rstmgr_tl_errors | 1.810s | 47.129us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| rstmgr_csr_hw_reset | 0.940s | 64.007us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 0.860s | 36.733us | 1 | 1 | 100.00 | |
| rstmgr_csr_aliasing | 1.150s | 40.655us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 0.880s | 42.041us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| rstmgr_csr_hw_reset | 0.940s | 64.007us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 0.860s | 36.733us | 1 | 1 | 100.00 | |
| rstmgr_csr_aliasing | 1.150s | 40.655us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 0.880s | 42.041us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| rstmgr_sec_cm | 29.820s | 6736.218us | 1 | 1 | 100.00 | |
| rstmgr_tl_intg_err | 2.280s | 327.916us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| rstmgr_sec_cm | 29.820s | 6736.218us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| rstmgr_sec_cm | 29.820s | 6736.218us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rstmgr_tl_intg_err | 2.280s | 327.916us | 1 | 1 | 100.00 | |
| sec_cm_scan_intersig_mubi | 1 | 1 | 100.00 | |||
| rstmgr_sec_cm_scan_intersig_mubi | 1.040s | 60.675us | 1 | 1 | 100.00 | |
| sec_cm_leaf_rst_bkgn_chk | 1 | 1 | 100.00 | |||
| rstmgr_leaf_rst_cnsty | 3.140s | 427.163us | 1 | 1 | 100.00 | |
| sec_cm_leaf_rst_shadow | 1 | 1 | 100.00 | |||
| rstmgr_leaf_rst_shadow_attack | 1.890s | 291.666us | 1 | 1 | 100.00 | |
| sec_cm_leaf_fsm_sparse | 1 | 1 | 100.00 | |||
| rstmgr_sec_cm | 29.820s | 6736.218us | 1 | 1 | 100.00 | |
| sec_cm_sw_rst_config_regwen | 1 | 1 | 100.00 | |||
| rstmgr_csr_rw | 0.860s | 36.733us | 1 | 1 | 100.00 | |
| sec_cm_dump_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| rstmgr_csr_rw | 0.860s | 36.733us | 1 | 1 | 100.00 | |