Simulation Results: rv_dm

 
24/11/2025 16:08:31 sha: e65c354 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 75.11
  • line
  • 90.64
  • cond
  • 74.09
  • toggle
  • 70.92
  • fsm
  • 53.12
  • branch
  • 74.79
  • assert
  • 96.16
  • group
  • 66.08
Validation stages
V1
93.55%
V2
64.29%
V2S
83.33%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 1.630s 869.723us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 0.950s 103.634us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 0.960s 269.469us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 9.550s 9576.478us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 1.890s 680.096us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 21.390s 9628.174us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 7.040s 7926.134us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 15.070s 25592.402us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 91.200s 50234.623us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 2.630s 1235.839us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 1.430s 440.320us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 0.760s 152.617us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 1.080s 422.405us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 0.970s 125.145us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 0.820s 835.245us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 0.880s 313.066us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 0.860s 236.042us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 2.630s 1235.839us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 1.110s 436.564us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 1.940s 739.704us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 0.760s 152.617us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 0.960s 177.681us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 1.440s 484.720us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 1.460s 152.631us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 49.000s 7413.632us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 53.710s 89601.343us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
rv_dm_csr_mem_rw_with_rand_reset 0.740s 68.597us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 53.710s 89601.343us 1 1 100.00
rv_dm_csr_rw 1.460s 152.631us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 0.750s 49.609us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 0.740s 177.451us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 1.630s 869.723us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 0.900s 416.543us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 0.900s 271.614us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 1.020s 552.287us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 2.760s 1735.280us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 570.620s 300000.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 355.630s 300000.000us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 267.710s 300000.000us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 564.450s 300000.000us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 0.720s 474.588us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 5.460s 2783.252us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 1.380s 403.059us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 0.810s 112.136us 0 1 0.00
tap_ctrl_transitions 1 2 50.00
rv_dm_tap_fsm_rand_reset 0.740s 16.867us 0 1 0.00
rv_dm_tap_fsm 7.880s 8577.564us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 0.810s 76.520us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 2.030s 1441.588us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 0.980s 173.925us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
rv_dm_tl_errors 0.970s 118.905us 0 1 0.00
tl_d_illegal_access 0 1 0.00
rv_dm_tl_errors 0.970s 118.905us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 53.710s 89601.343us 1 1 100.00
rv_dm_csr_hw_reset 1.440s 484.720us 1 1 100.00
rv_dm_csr_rw 1.460s 152.631us 1 1 100.00
rv_dm_same_csr_outstanding 2.750s 306.433us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 53.710s 89601.343us 1 1 100.00
rv_dm_csr_hw_reset 1.440s 484.720us 1 1 100.00
rv_dm_csr_rw 1.460s 152.631us 1 1 100.00
rv_dm_same_csr_outstanding 2.750s 306.433us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_tl_intg_err 11.480s 2403.194us 1 1 100.00
rv_dm_sec_cm 1.100s 1765.851us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 11.480s 2403.194us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 5.460s 2783.252us 1 1 100.00
rv_dm_debug_disabled 0.880s 154.900us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 5.460s 2783.252us 1 1 100.00
rv_dm_debug_disabled 0.880s 154.900us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 1.630s 869.723us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 0 1 0.00
rv_dm_buffered_enable 0.910s 176.257us 0 1 0.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.780s 68.617us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.780s 68.617us 1 1 100.00
sec_cm_exec_ctrl_mubi 0 1 0.00
rv_dm_buffered_enable 0.910s 176.257us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 0.720s 34.095us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 590.160s 300000.000us 0 1 0.00