Simulation Results: spi_host

 
24/11/2025 16:08:31 sha: e65c354 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • score
  • 95.52
  • block
  • 96.59
  • branch
  • 92.85
  • statement
  • 98.41
  • expression
  • 91.89
  • toggle
  • 88.02
  • fsm
  • 100.0
  • assertion
  • 93.54
  • covergroup
  • 88.33
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 27.000s 1893.863us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 16.938us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 37.794us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 89.762us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 54.357us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 28.312us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 37.794us 1 1 100.00
spi_host_csr_aliasing 1.000s 54.357us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 27.573us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 18.722us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 6.000s 18.434us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 237.578us 1 1 100.00
spi_host_error_cmd 1.000s 112.431us 1 1 100.00
spi_host_event 5.000s 403.429us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 10.000s 32.209us 1 1 100.00
speed 1 1 100.00
spi_host_speed 10.000s 32.209us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 10.000s 32.209us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 4.000s 41.362us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 66.179us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 10.000s 32.209us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 10.000s 32.209us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 27.000s 1893.863us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 27.000s 1893.863us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 214.652us 1 1 100.00
spien 1 1 100.00
spi_host_spien 2.000s 85.171us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 27.000s 921.801us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 409.499us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 237.578us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 27.227us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 24.930us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 138.496us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 138.496us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 16.938us 1 1 100.00
spi_host_csr_rw 2.000s 37.794us 1 1 100.00
spi_host_csr_aliasing 1.000s 54.357us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 67.912us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 16.938us 1 1 100.00
spi_host_csr_rw 2.000s 37.794us 1 1 100.00
spi_host_csr_aliasing 1.000s 54.357us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 67.912us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 2.000s 967.439us 1 1 100.00
spi_host_tl_intg_err 1.000s 178.213us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 178.213us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 92.000s 5693.639us 1 1 100.00