Simulation Results: sram_ctrl

 
24/11/2025 16:08:31 sha: e65c354 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 95.6
  • line
  • 98.84
  • cond
  • 91.8
  • toggle
  • 90.71
  • fsm
  • 100.0
  • branch
  • 96.53
  • assert
  • 95.55
  • group
  • 95.73
Validation stages
V1
100.00%
V2
100.00%
V2S
70.83%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 8.500s 767.644us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.900s 17.347us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.740s 33.590us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.160s 115.249us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 18.298us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.160s 371.867us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.740s 33.590us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 18.298us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 97.830s 2064.328us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 113.900s 5623.436us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 225.030s 10057.691us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 209.880s 4605.558us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1107.220s 25694.730us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 563.060s 29887.642us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 38.990s 34475.994us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 507.270s 135047.077us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 58.300s 909.870us 1 1 100.00
sram_ctrl_partial_access_b2b 362.490s 82351.027us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 8.210s 723.927us 1 1 100.00
sram_ctrl_throughput_w_partial_write 24.960s 3067.587us 1 1 100.00
sram_ctrl_throughput_w_readback 8.510s 761.524us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 534.950s 3086.118us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.420s 362.956us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1972.060s 63728.292us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.830s 13.487us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.850s 46.389us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.850s 46.389us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.900s 17.347us 1 1 100.00
sram_ctrl_csr_rw 0.740s 33.590us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 18.298us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.880s 29.187us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.900s 17.347us 1 1 100.00
sram_ctrl_csr_rw 0.740s 33.590us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 18.298us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.880s 29.187us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.820s 14766.092us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.780s 2.123us 0 1 0.00
sram_ctrl_tl_intg_err 2.300s 876.353us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.780s 2.123us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.300s 876.353us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 534.950s 3086.118us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 534.950s 3086.118us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.740s 33.590us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 507.270s 135047.077us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 507.270s 135047.077us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 507.270s 135047.077us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 38.990s 34475.994us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.840s 7354.982us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.820s 14766.092us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3.530s 687.796us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 8.500s 767.644us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 8.500s 767.644us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 507.270s 135047.077us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.780s 2.123us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 38.990s 34475.994us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.780s 2.123us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.780s 2.123us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 8.500s 767.644us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.780s 2.123us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 35.850s 762.819us 1 1 100.00