Simulation Results: sram_ctrl

 
24/11/2025 16:08:31 sha: e65c354 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 92.47
  • line
  • 97.86
  • cond
  • 92.53
  • toggle
  • 90.19
  • fsm
  • 80.95
  • branch
  • 95.71
  • assert
  • 95.79
  • group
  • 94.25
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 7.780s 677.862us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.930s 24.370us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.740s 42.342us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.840s 173.652us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.740s 34.702us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.190s 125.676us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.740s 42.342us 1 1 100.00
sram_ctrl_csr_aliasing 0.740s 34.702us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.280s 1561.632us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.490s 93.076us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 490.180s 12956.974us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 138.270s 7540.509us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 39.820s 12000.621us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 563.390s 4535.914us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.530s 737.849us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 358.040s 2406.215us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 12.500s 477.087us 1 1 100.00
sram_ctrl_partial_access_b2b 398.100s 7029.178us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 13.230s 153.605us 1 1 100.00
sram_ctrl_throughput_w_partial_write 57.710s 295.053us 1 1 100.00
sram_ctrl_throughput_w_readback 12.280s 544.287us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 251.780s 10035.859us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.920s 281.991us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2089.560s 60556.275us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.630s 19.672us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.910s 129.354us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.910s 129.354us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.930s 24.370us 1 1 100.00
sram_ctrl_csr_rw 0.740s 42.342us 1 1 100.00
sram_ctrl_csr_aliasing 0.740s 34.702us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.850s 30.729us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.930s 24.370us 1 1 100.00
sram_ctrl_csr_rw 0.740s 42.342us 1 1 100.00
sram_ctrl_csr_aliasing 0.740s 34.702us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.850s 30.729us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.730s 796.735us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.650s 12.497us 0 1 0.00
sram_ctrl_tl_intg_err 2.030s 179.016us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.650s 12.497us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.030s 179.016us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 251.780s 10035.859us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 251.780s 10035.859us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.740s 42.342us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 358.040s 2406.215us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 358.040s 2406.215us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 358.040s 2406.215us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.530s 737.849us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.080s 132.794us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.730s 796.735us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 0.890s 111.460us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 7.780s 677.862us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 7.780s 677.862us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 358.040s 2406.215us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.650s 12.497us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.530s 737.849us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.650s 12.497us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.650s 12.497us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 7.780s 677.862us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.650s 12.497us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 51.100s 5358.931us 1 1 100.00