Simulation Results: uart

 
24/11/2025 16:08:31 sha: e65c354 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 86.94
  • line
  • 98.86
  • cond
  • 93.0
  • toggle
  • 91.55
  • fsm
  • None
  • branch
  • 96.27
  • assert
  • 97.12
  • group
  • 44.81
Validation stages
V1
100.00%
V2
91.18%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.760s 517.642us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.870s 31.755us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.880s 14.171us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.610s 166.110us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.810s 30.661us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.950s 33.512us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.880s 14.171us 1 1 100.00
uart_csr_aliasing 0.810s 30.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 56.710s 58690.580us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.760s 517.642us 1 1 100.00
uart_tx_rx 56.710s 58690.580us 1 1 100.00
parity_error 2 2 100.00
uart_intr 21.280s 10696.272us 1 1 100.00
uart_rx_parity_err 51.910s 19844.547us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 56.710s 58690.580us 1 1 100.00
uart_intr 21.280s 10696.272us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 25.660s 70635.297us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 46.670s 115121.809us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 27.230s 39423.302us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 21.280s 10696.272us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 21.280s 10696.272us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 21.280s 10696.272us 1 1 100.00
perf 0 1 0.00
uart_perf 290.510s 18231.657us 0 1 0.00
sys_loopback 1 1 100.00
uart_loopback 5.060s 5571.626us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 5.060s 5571.626us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 22.930s 65549.192us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.440s 2614.315us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.180s 916.548us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 7.110s 5364.984us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 123.170s 85803.915us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 44.890s 32046.842us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.810s 125.507us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.670s 18.420us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.380s 33.825us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.380s 33.825us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.870s 31.755us 1 1 100.00
uart_csr_rw 0.880s 14.171us 1 1 100.00
uart_csr_aliasing 0.810s 30.661us 1 1 100.00
uart_same_csr_outstanding 0.940s 31.438us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.870s 31.755us 1 1 100.00
uart_csr_rw 0.880s 14.171us 1 1 100.00
uart_csr_aliasing 0.810s 30.661us 1 1 100.00
uart_same_csr_outstanding 0.940s 31.438us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_tl_intg_err 1.240s 53.770us 1 1 100.00
uart_sec_cm 1.200s 62.332us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.240s 53.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 28.740s 11019.776us 1 1 100.00