| chip_sw_spi_device_flash_mode |
0 |
1 |
0.00 |
|
chip_sw_uart_tx_rx_bootstrap |
87.331s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_spi_device_pass_through |
1 |
1 |
100.00 |
|
chip_sw_spi_device_pass_through |
1943.220s |
3280.015us |
1 |
1 |
100.00
|
| chip_sw_spi_device_pass_through_collision |
0 |
1 |
0.00 |
|
chip_sw_spi_device_pass_through_collision |
279.940s |
298.073us |
0 |
1 |
0.00
|
| chip_sw_spi_device_tpm |
0 |
1 |
0.00 |
|
chip_sw_spi_device_tpm |
61.981s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_spi_host_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_spi_host_tx_rx |
54.283s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_i2c_host_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_i2c_host_tx_rx |
62.103s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_i2c_device_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_i2c_device_tx_rx |
73.569s |
0.000us |
0 |
1 |
0.00
|
| chip_pin_mux |
0 |
1 |
0.00 |
|
chip_padctrl_attributes |
2.770s |
0.000us |
0 |
1 |
0.00
|
| chip_padctrl_attributes |
0 |
1 |
0.00 |
|
chip_padctrl_attributes |
2.770s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sleep_pin_wake |
0 |
1 |
0.00 |
|
chip_sw_sleep_pin_wake |
131.032s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sleep_pin_retention |
0 |
1 |
0.00 |
|
chip_sw_sleep_pin_retention |
125.419s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_data_integrity |
0 |
1 |
0.00 |
|
chip_sw_data_integrity_escalation |
121.250s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_instruction_integrity |
0 |
1 |
0.00 |
|
chip_sw_data_integrity_escalation |
121.250s |
0.000us |
0 |
1 |
0.00
|
| chip_jtag_csr_rw |
0 |
1 |
0.00 |
|
chip_jtag_csr_rw |
124.760s |
117.018us |
0 |
1 |
0.00
|
| chip_jtag_mem_access |
0 |
1 |
0.00 |
|
chip_jtag_mem_access |
113.430s |
117.033us |
0 |
1 |
0.00
|
| chip_rv_dm_ndm_reset_req |
1 |
1 |
100.00 |
|
chip_rv_dm_ndm_reset_req |
261.360s |
272.306us |
1 |
1 |
100.00
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted |
0 |
1 |
0.00 |
|
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted |
10.220s |
0.000us |
0 |
1 |
0.00
|
| chip_rv_dm_access_after_wakeup |
0 |
1 |
0.00 |
|
chip_sw_rv_dm_access_after_wakeup |
11.178s |
0.000us |
0 |
1 |
0.00
|
| chip_rv_dm_lc_disabled |
0 |
1 |
0.00 |
|
chip_rv_dm_lc_disabled |
95.220s |
130.180us |
0 |
1 |
0.00
|
| chip_sw_timer |
1 |
1 |
100.00 |
|
chip_sw_rv_timer_irq |
263.510s |
248.720us |
1 |
1 |
100.00
|
| chip_sw_aon_timer_wakeup_irq |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_irq |
415.460s |
542.529us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_wdog_bark_irq |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_irq |
415.460s |
542.529us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_wdog_lc_escalate |
1 |
1 |
100.00 |
|
chip_sw_aon_timer_wdog_lc_escalate |
399.070s |
348.690us |
1 |
1 |
100.00
|
| chip_sw_aon_timer_wdog_bite_reset |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
213.430s |
164.359us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_sleep_wdog_bite_reset |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
213.430s |
164.359us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_sleep_wdog_sleep_pause |
1 |
1 |
100.00 |
|
chip_sw_aon_timer_sleep_wdog_sleep_pause |
288.420s |
2271.441us |
1 |
1 |
100.00
|
| chip_sw_plic_sw_irq |
1 |
1 |
100.00 |
|
chip_sw_plic_sw_irq |
159.150s |
145.465us |
1 |
1 |
100.00
|
| chip_sw_clkmgr_idle_trans |
4 |
4 |
100.00 |
|
chip_sw_otbn_randomness |
256.350s |
225.694us |
1 |
1 |
100.00
|
|
chip_sw_aes_idle |
171.320s |
147.283us |
1 |
1 |
100.00
|
|
chip_sw_hmac_enc_idle |
184.650s |
161.508us |
1 |
1 |
100.00
|
|
chip_sw_kmac_idle |
161.700s |
145.023us |
1 |
1 |
100.00
|
| chip_sw_clkmgr_off_trans |
0 |
4 |
0.00 |
|
chip_sw_clkmgr_off_aes_trans |
170.530s |
165.648us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_hmac_trans |
186.220s |
165.648us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_kmac_trans |
160.540s |
165.648us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_otbn_trans |
169.690s |
165.648us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_jitter |
1 |
7 |
14.29 |
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
41.820s |
10.240us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en |
36.050s |
10.200us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en |
37.400s |
10.400us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
37.810s |
10.220us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
40.530s |
10.140us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
9.684s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_jitter |
161.380s |
141.843us |
1 |
1 |
100.00
|
| chip_sw_clkmgr_extended_range |
1 |
8 |
12.50 |
|
chip_sw_clkmgr_jitter_reduced_freq |
318.240s |
1779.427us |
1 |
1 |
100.00
|
|
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq |
36.830s |
10.220us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en_reduced_freq |
36.940s |
10.360us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en_reduced_freq |
47.610s |
10.120us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq |
39.700s |
10.380us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq |
38.280s |
10.300us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq |
40.310s |
10.360us |
0 |
1 |
0.00
|
|
chip_sw_csrng_edn_concurrency_reduced_freq |
39.200s |
10.180us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_deep_sleep_frequency |
0 |
1 |
0.00 |
|
chip_sw_ast_clk_outputs |
10.012s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_sleep_frequency |
0 |
1 |
0.00 |
|
chip_sw_clkmgr_sleep_frequency |
9.791s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_reset_frequency |
0 |
1 |
0.00 |
|
chip_sw_clkmgr_reset_frequency |
12.941s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
933.140s |
905.420us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_external_full_reset |
1 |
1 |
100.00 |
|
chip_sw_pwrmgr_full_aon_reset |
347.930s |
499.466us |
1 |
1 |
100.00
|
| chip_sw_pwrmgr_sleep_all_reset_reqs |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
213.430s |
164.359us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_wdog_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_wdog_reset |
10.454s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_aon_power_glitch_reset |
1 |
1 |
100.00 |
|
chip_sw_pwrmgr_full_aon_reset |
347.930s |
499.466us |
1 |
1 |
100.00
|
| chip_sw_pwrmgr_main_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_main_power_glitch_reset |
11.356s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_random_sleep_power_glitch_reset |
10.745s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_deep_sleep_power_glitch_reset |
19.511s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_sleep_power_glitch_reset |
18.177s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_sleep_disabled |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_sleep_disabled |
11.761s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
933.140s |
905.420us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sys_reset_info |
1 |
1 |
100.00 |
|
chip_rv_dm_ndm_reset_req |
261.360s |
272.306us |
1 |
1 |
100.00
|
| chip_sw_rstmgr_cpu_info |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
374.060s |
375.168us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sw_req_reset |
1 |
1 |
100.00 |
|
chip_sw_rstmgr_sw_req |
272.050s |
267.488us |
1 |
1 |
100.00
|
| chip_sw_rstmgr_alert_info |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_alert_info |
298.660s |
290.013us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sw_rst |
1 |
1 |
100.00 |
|
chip_sw_rstmgr_sw_rst |
169.620s |
144.123us |
1 |
1 |
100.00
|
| chip_sw_rstmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
933.140s |
905.420us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_alerts |
0 |
1 |
0.00 |
|
chip_sw_alert_test |
10.388s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_escalations |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_escalation |
10.266s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_all_escalation_resets |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
933.140s |
905.420us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_entropy |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_entropy |
10.224s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_crashdump |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_alert_info |
298.660s |
290.013us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_ping_timeout |
1 |
1 |
100.00 |
|
chip_sw_alert_handler_ping_timeout |
268.990s |
291.959us |
1 |
1 |
100.00
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_sleep_mode_alerts |
11.846s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_sleep_mode_pings |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_sleep_mode_pings |
9.834s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_clock_off |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_clkoff |
11.168s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_reset_toggle |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_reset_toggle |
10.512s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_reverse_ping_in_deep_sleep |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_reverse_ping_in_deep_sleep |
12.244s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_alert_handler_escalation |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_escalation |
10.266s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_jtag_access |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
10.452s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_otp_hw_cfg |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_otp_hw_cfg |
9.631s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_init |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
10.452s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_transitions |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
10.452s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_kmac_req |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
10.452s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_key_div |
0 |
1 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation_prod |
290.750s |
267.800us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_broadcast |
2 |
10 |
20.00 |
|
chip_prim_tl_access |
667.820s |
977.630us |
1 |
1 |
100.00
|
|
chip_rv_dm_lc_disabled |
95.220s |
130.180us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_test_unlocked0 |
21.263s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_dev |
35.500s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_prod |
10.377s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_rma |
11.973s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_ctrl_transition |
10.452s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation |
276.120s |
267.575us |
0 |
1 |
0.00
|
|
chip_sw_rom_ctrl_integrity_check |
749.940s |
1266.567us |
1 |
1 |
100.00
|
|
chip_sw_sram_ctrl_execution_main |
9.525s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_aes_enc |
1 |
2 |
50.00 |
|
chip_sw_aes_enc |
188.180s |
157.124us |
1 |
1 |
100.00
|
|
chip_sw_aes_enc_jitter_en |
36.050s |
10.200us |
0 |
1 |
0.00
|
| chip_sw_aes_entropy |
1 |
1 |
100.00 |
|
chip_sw_aes_entropy |
164.580s |
145.881us |
1 |
1 |
100.00
|
| chip_sw_aes_idle |
1 |
1 |
100.00 |
|
chip_sw_aes_idle |
171.320s |
147.283us |
1 |
1 |
100.00
|
| chip_sw_hmac_enc |
1 |
2 |
50.00 |
|
chip_sw_hmac_enc |
171.980s |
156.430us |
1 |
1 |
100.00
|
|
chip_sw_hmac_enc_jitter_en |
37.400s |
10.400us |
0 |
1 |
0.00
|
| chip_sw_hmac_idle |
1 |
1 |
100.00 |
|
chip_sw_hmac_enc_idle |
184.650s |
161.508us |
1 |
1 |
100.00
|
| chip_sw_kmac_enc |
2 |
3 |
66.67 |
|
chip_sw_kmac_mode_cshake |
169.490s |
148.954us |
1 |
1 |
100.00
|
|
chip_sw_kmac_mode_kmac |
226.670s |
172.106us |
1 |
1 |
100.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
40.530s |
10.140us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_keymgr |
0 |
1 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation |
276.120s |
267.575us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_lc |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
10.452s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_rom |
0 |
1 |
0.00 |
|
chip_sw_kmac_app_rom |
33.820s |
10.240us |
0 |
1 |
0.00
|
| chip_sw_kmac_entropy |
1 |
1 |
100.00 |
|
chip_sw_kmac_entropy |
228.960s |
184.897us |
1 |
1 |
100.00
|
| chip_sw_kmac_idle |
1 |
1 |
100.00 |
|
chip_sw_kmac_idle |
161.700s |
145.023us |
1 |
1 |
100.00
|
| chip_sw_entropy_src_csrng |
1 |
1 |
100.00 |
|
chip_sw_entropy_src_csrng |
378.480s |
278.033us |
1 |
1 |
100.00
|
| chip_sw_csrng_edn_cmd |
1 |
1 |
100.00 |
|
chip_sw_entropy_src_csrng |
378.480s |
278.033us |
1 |
1 |
100.00
|
| chip_sw_csrng_fuse_en_sw_app_read |
0 |
1 |
0.00 |
|
chip_sw_csrng_fuse_en_sw_app_read_test |
11.627s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_csrng_known_answer_tests |
1 |
1 |
100.00 |
|
chip_sw_csrng_kat_test |
184.070s |
156.815us |
1 |
1 |
100.00
|
| chip_sw_edn_entropy_reqs |
1 |
1 |
100.00 |
|
chip_sw_csrng_edn_concurrency |
670.330s |
541.435us |
1 |
1 |
100.00
|
| chip_sw_keymgr_dpe_key_derivation |
0 |
2 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation |
276.120s |
267.575us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
37.810s |
10.220us |
0 |
1 |
0.00
|
| chip_sw_otbn_op |
1 |
2 |
50.00 |
|
chip_sw_otbn_ecdsa_op_irq |
2292.390s |
1460.344us |
1 |
1 |
100.00
|
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
41.820s |
10.240us |
0 |
1 |
0.00
|
| chip_sw_otbn_rnd_entropy |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
256.350s |
225.694us |
1 |
1 |
100.00
|
| chip_sw_otbn_urnd_entropy |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
256.350s |
225.694us |
1 |
1 |
100.00
|
| chip_sw_otbn_idle |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
256.350s |
225.694us |
1 |
1 |
100.00
|
| chip_sw_otbn_mem_scramble |
1 |
1 |
100.00 |
|
chip_sw_otbn_mem_scramble |
372.540s |
264.613us |
1 |
1 |
100.00
|
| chip_sw_rom_access |
1 |
1 |
100.00 |
|
chip_sw_rom_ctrl_integrity_check |
749.940s |
1266.567us |
1 |
1 |
100.00
|
| chip_sw_rom_ctrl_integrity_check |
1 |
1 |
100.00 |
|
chip_sw_rom_ctrl_integrity_check |
749.940s |
1266.567us |
1 |
1 |
100.00
|
| chip_sw_sram_scrambled_access |
1 |
2 |
50.00 |
|
chip_sw_sram_ctrl_scrambled_access |
340.680s |
314.044us |
1 |
1 |
100.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
9.684s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sram_execution |
0 |
1 |
0.00 |
|
chip_sw_sram_ctrl_execution_main |
9.525s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sram_lc_escalation |
0 |
2 |
0.00 |
|
chip_sw_all_escalation_resets |
933.140s |
905.420us |
0 |
1 |
0.00
|
|
chip_sw_data_integrity_escalation |
121.250s |
0.000us |
0 |
1 |
0.00
|
| chip_otp_ctrl_init |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
10.452s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_keys |
3 |
4 |
75.00 |
|
chip_sw_otbn_mem_scramble |
372.540s |
264.613us |
1 |
1 |
100.00
|
|
chip_sw_keymgr_dpe_key_derivation |
276.120s |
267.575us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access |
340.680s |
314.044us |
1 |
1 |
100.00
|
|
chip_sw_rv_core_ibex_icache_invalidate |
161.780s |
167.887us |
1 |
1 |
100.00
|
| chip_sw_otp_ctrl_entropy |
3 |
4 |
75.00 |
|
chip_sw_otbn_mem_scramble |
372.540s |
264.613us |
1 |
1 |
100.00
|
|
chip_sw_keymgr_dpe_key_derivation |
276.120s |
267.575us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access |
340.680s |
314.044us |
1 |
1 |
100.00
|
|
chip_sw_rv_core_ibex_icache_invalidate |
161.780s |
167.887us |
1 |
1 |
100.00
|
| chip_sw_otp_ctrl_program |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
10.452s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_program_error |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_program_error |
9.751s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_hw_cfg |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_otp_hw_cfg |
9.631s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_lc_signals |
1 |
6 |
16.67 |
|
chip_prim_tl_access |
667.820s |
977.630us |
1 |
1 |
100.00
|
|
chip_sw_otp_ctrl_lc_signals_test_unlocked0 |
21.263s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_dev |
35.500s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_prod |
10.377s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_rma |
11.973s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_ctrl_transition |
10.452s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_prim_tl_access |
1 |
1 |
100.00 |
|
chip_prim_tl_access |
667.820s |
977.630us |
1 |
1 |
100.00
|
| chip_sw_otp_ctrl_nvm_cnt |
0 |
1 |
0.00 |
|
chip_sw_otp_ctrl_nvm_cnt |
21.440s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_sw_parts |
0 |
1 |
0.00 |
|
chip_sw_otp_ctrl_sw_parts |
11.369s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_ast_clk_outputs |
0 |
1 |
0.00 |
|
chip_sw_ast_clk_outputs |
10.012s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_ast_sys_clk_jitter |
1 |
7 |
14.29 |
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
41.820s |
10.240us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en |
36.050s |
10.200us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en |
37.400s |
10.400us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
37.810s |
10.220us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
40.530s |
10.140us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
9.684s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_jitter |
161.380s |
141.843us |
1 |
1 |
100.00
|
| chip_sw_soc_proxy_external_reset_requests |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_smoketest |
176.200s |
143.552us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_external_irqs |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_smoketest |
176.200s |
143.552us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_external_wakeup_requests |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_external_wakeup |
178.880s |
138.844us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_gpios |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_gpios |
143.790s |
136.449us |
0 |
1 |
0.00
|
| chip_sw_nmi_irq |
0 |
1 |
0.00 |
|
chip_sw_rv_core_ibex_nmi_irq |
363.600s |
251.595us |
0 |
1 |
0.00
|
| chip_sw_rv_core_ibex_rnd |
1 |
1 |
100.00 |
|
chip_sw_rv_core_ibex_rnd |
188.930s |
160.191us |
1 |
1 |
100.00
|
| chip_sw_rv_core_ibex_address_translation |
1 |
1 |
100.00 |
|
chip_sw_rv_core_ibex_address_translation |
178.330s |
164.789us |
1 |
1 |
100.00
|
| chip_sw_rv_core_ibex_icache_scrambled_access |
1 |
1 |
100.00 |
|
chip_sw_rv_core_ibex_icache_invalidate |
161.780s |
167.887us |
1 |
1 |
100.00
|
| chip_sw_rv_core_ibex_fault_dump |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
374.060s |
375.168us |
0 |
1 |
0.00
|
| chip_sw_rv_core_ibex_double_fault |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
374.060s |
375.168us |
0 |
1 |
0.00
|
| chip_sw_smoketest |
14 |
14 |
100.00 |
|
chip_sw_aes_smoketest |
135.080s |
157.144us |
1 |
1 |
100.00
|
|
chip_sw_aon_timer_smoketest |
146.700s |
163.219us |
1 |
1 |
100.00
|
|
chip_sw_clkmgr_smoketest |
131.100s |
142.982us |
1 |
1 |
100.00
|
|
chip_sw_csrng_smoketest |
131.400s |
144.800us |
1 |
1 |
100.00
|
|
chip_sw_gpio_smoketest |
155.490s |
165.795us |
1 |
1 |
100.00
|
|
chip_sw_hmac_smoketest |
172.820s |
181.983us |
1 |
1 |
100.00
|
|
chip_sw_kmac_smoketest |
153.150s |
171.093us |
1 |
1 |
100.00
|
|
chip_sw_otbn_smoketest |
196.430s |
209.966us |
1 |
1 |
100.00
|
|
chip_sw_otp_ctrl_smoketest |
140.840s |
146.968us |
1 |
1 |
100.00
|
|
chip_sw_rv_plic_smoketest |
132.960s |
145.047us |
1 |
1 |
100.00
|
|
chip_sw_rv_timer_smoketest |
179.320s |
248.759us |
1 |
1 |
100.00
|
|
chip_sw_rstmgr_smoketest |
133.630s |
141.601us |
1 |
1 |
100.00
|
|
chip_sw_sram_ctrl_smoketest |
128.700s |
145.499us |
1 |
1 |
100.00
|
|
chip_sw_uart_smoketest |
143.460s |
157.675us |
1 |
1 |
100.00
|
| chip_sw_rom_functests |
0 |
1 |
0.00 |
|
rom_keymgr_functest |
10.343s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_signed |
0 |
1 |
0.00 |
|
chip_sw_uart_smoketest_signed |
9.789s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_boot |
0 |
1 |
0.00 |
|
chip_sw_uart_tx_rx_bootstrap |
87.331s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_secure_boot |
0 |
1 |
0.00 |
|
base_rom_e2e_smoke |
12.609s |
0.000us |
0 |
1 |
0.00
|
| chip_lc_scrap |
4 |
4 |
100.00 |
|
chip_sw_lc_ctrl_rma_to_scrap |
177.420s |
200.635us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_raw_to_scrap |
206.540s |
221.174us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_test_locked0_to_scrap |
181.170s |
225.643us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_rand_to_scrap |
188.280s |
221.744us |
1 |
1 |
100.00
|
| chip_lc_test_locked |
0 |
2 |
0.00 |
|
chip_rv_dm_lc_disabled |
95.220s |
130.180us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_testunlocks |
9.422s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_walkthrough |
0 |
5 |
0.00 |
|
chip_sw_lc_walkthrough_dev |
11.091s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_prod |
10.948s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_prodend |
17.942s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_rma |
9.450s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_testunlocks |
9.422s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_volatile_raw_unlock |
2 |
3 |
66.67 |
|
chip_sw_lc_ctrl_volatile_raw_unlock |
442.800s |
515.453us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz |
588.170s |
757.036us |
1 |
1 |
100.00
|
|
rom_volatile_raw_unlock |
9.429s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_rom_raw_unlock |
0 |
1 |
0.00 |
|
rom_raw_unlock |
10.165s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_exit_test_unlocked_bootstrap |
0 |
1 |
0.00 |
|
chip_sw_exit_test_unlocked_bootstrap |
92.874s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_inject_scramble_seed |
0 |
1 |
0.00 |
|
chip_sw_inject_scramble_seed |
92.772s |
0.000us |
0 |
1 |
0.00
|
| tl_d_oob_addr_access |
0 |
1 |
0.00 |
|
chip_tl_errors |
113.540s |
118.037us |
0 |
1 |
0.00
|
| tl_d_illegal_access |
0 |
1 |
0.00 |
|
chip_tl_errors |
113.540s |
118.037us |
0 |
1 |
0.00
|
| tl_d_outstanding_access |
0 |
2 |
0.00 |
|
chip_csr_aliasing |
10.120s |
0.000us |
0 |
1 |
0.00
|
|
chip_same_csr_outstanding |
9.220s |
0.000us |
0 |
1 |
0.00
|
| tl_d_partial_access |
0 |
2 |
0.00 |
|
chip_csr_aliasing |
10.120s |
0.000us |
0 |
1 |
0.00
|
|
chip_same_csr_outstanding |
9.220s |
0.000us |
0 |
1 |
0.00
|
| xbar_base_random_sequence |
1 |
1 |
100.00 |
|
xbar_random |
54.140s |
43.038us |
1 |
1 |
100.00
|
| xbar_random_delay |
6 |
6 |
100.00 |
|
xbar_smoke_zero_delays |
8.970s |
12.070us |
1 |
1 |
100.00
|
|
xbar_smoke_large_delays |
256.920s |
2086.537us |
1 |
1 |
100.00
|
|
xbar_smoke_slow_rsp |
306.770s |
1739.273us |
1 |
1 |
100.00
|
|
xbar_random_zero_delays |
93.380s |
75.206us |
1 |
1 |
100.00
|
|
xbar_random_large_delays |
193.570s |
1527.289us |
1 |
1 |
100.00
|
|
xbar_random_slow_rsp |
1705.610s |
9827.314us |
1 |
1 |
100.00
|
| xbar_unmapped_address |
2 |
2 |
100.00 |
|
xbar_unmapped_addr |
39.460s |
62.414us |
1 |
1 |
100.00
|
|
xbar_error_and_unmapped_addr |
44.920s |
29.552us |
1 |
1 |
100.00
|
| xbar_error_cases |
2 |
2 |
100.00 |
|
xbar_error_random |
169.860s |
470.088us |
1 |
1 |
100.00
|
|
xbar_error_and_unmapped_addr |
44.920s |
29.552us |
1 |
1 |
100.00
|
| xbar_all_access_same_device |
2 |
2 |
100.00 |
|
xbar_access_same_device |
73.290s |
176.926us |
1 |
1 |
100.00
|
|
xbar_access_same_device_slow_rsp |
2456.860s |
14762.759us |
1 |
1 |
100.00
|
| xbar_all_hosts_use_same_source_id |
1 |
1 |
100.00 |
|
xbar_same_source |
61.390s |
148.591us |
1 |
1 |
100.00
|
| xbar_stress_all |
2 |
2 |
100.00 |
|
xbar_stress_all |
80.170s |
183.293us |
1 |
1 |
100.00
|
|
xbar_stress_all_with_error |
220.660s |
570.819us |
1 |
1 |
100.00
|
| xbar_stress_with_reset |
2 |
2 |
100.00 |
|
xbar_stress_all_with_rand_reset |
1133.010s |
2313.929us |
1 |
1 |
100.00
|
|
xbar_stress_all_with_reset_error |
2198.040s |
1737.334us |
1 |
1 |
100.00
|
| rom_e2e_smoke |
0 |
1 |
0.00 |
|
rom_e2e_smoke |
10.106s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_shutdown_output |
0 |
1 |
0.00 |
|
rom_e2e_shutdown_output |
9.940s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_shutdown_exception_c |
0 |
1 |
0.00 |
|
rom_e2e_shutdown_exception_c |
10.336s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_boot_policy_valid |
0 |
15 |
0.00 |
|
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 |
10.132s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_dev |
9.505s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_prod |
10.761s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_prod_end |
10.967s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_rma |
9.906s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 |
11.516s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_dev |
10.559s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_prod |
11.125s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end |
9.993s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_rma |
10.118s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 |
69.298s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_dev |
67.075s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_prod |
75.652s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end |
59.173s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_rma |
56.199s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_sigverify_always |
0 |
15 |
0.00 |
|
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 |
64.516s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_dev |
67.785s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_prod |
64.840s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_prod_end |
69.202s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_rma |
56.486s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 |
52.076s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_dev |
57.135s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_prod |
54.434s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end |
46.981s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_rma |
52.458s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 |
13.942s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_dev |
10.235s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_prod |
21.532s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end |
22.445s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_rma |
18.212s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_asm_init |
0 |
5 |
0.00 |
|
rom_e2e_asm_init_test_unlocked0 |
21.439s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_dev |
11.717s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_prod |
11.186s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_prod_end |
11.243s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_rma |
14.821s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_keymgr_init |
0 |
3 |
0.00 |
|
rom_e2e_keymgr_init_rom_ext_meas |
10.620s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_keymgr_init_rom_ext_no_meas |
9.663s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_keymgr_init_rom_ext_invalid_meas |
10.837s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_static_critical |
0 |
1 |
0.00 |
|
rom_e2e_static_critical |
11.245s |
0.000us |
0 |
1 |
0.00
|