Simulation Results: clkmgr

 
25/11/2025 16:03:05 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 85.32
  • line
  • 91.83
  • cond
  • 85.97
  • toggle
  • 98.87
  • fsm
  • 62.5
  • branch
  • 94.9
  • assert
  • 91.32
  • group
  • 71.82
Validation stages
V1
62.50%
V2
68.42%
V2S
76.47%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.820s 21.680us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.710s 18.770us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.770s 22.157us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.630s 69.144us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.680s 9.850us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.290s 59.028us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.770s 22.157us 1 1 100.00
clkmgr_csr_aliasing 0.680s 9.850us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.780s 20.203us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.940s 37.917us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.830s 35.689us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.820s 21.680us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 1.040s 46.159us 1 1 100.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.660s 5.303us 0 1 0.00
frequency_overflow 1 1 100.00
clkmgr_frequency 1.040s 46.159us 1 1 100.00
stress_all 0 1 0.00
clkmgr_stress_all 2.530s 212.038us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.770s 15.466us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.720s 77.464us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.720s 77.464us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.710s 18.770us 1 1 100.00
clkmgr_csr_rw 0.770s 22.157us 1 1 100.00
clkmgr_csr_aliasing 0.680s 9.850us 0 1 0.00
clkmgr_same_csr_outstanding 0.730s 15.332us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.710s 18.770us 1 1 100.00
clkmgr_csr_rw 0.770s 22.157us 1 1 100.00
clkmgr_csr_aliasing 0.680s 9.850us 0 1 0.00
clkmgr_same_csr_outstanding 0.730s 15.332us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 2.260s 180.187us 1 1 100.00
clkmgr_tl_intg_err 1.210s 64.250us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.110s 35.773us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.110s 35.773us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.110s 35.773us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.110s 35.773us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.630s 2.270us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 1.210s 64.250us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 1.040s 46.159us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.660s 5.303us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.110s 35.773us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.490s 89.641us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.770s 22.157us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 2.260s 180.187us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.770s 22.157us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.770s 22.157us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 2.260s 180.187us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.700s 4.646us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.820s 17.441us 0 1 0.00