Simulation Results: dma

 
25/11/2025 16:03:05 sha: 3424e7f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • score
  • 89.44
  • block
  • 97.34
  • branch
  • 95.76
  • statement
  • 96.85
  • expression
  • 95.59
  • toggle
  • 83.12
  • fsm
  • 91.55
  • assertion
  • 95.97
  • covergroup
  • 63.35
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 6.000s 318.760us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 293.125us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 1763.219us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 53.203us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 13.567us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 6.000s 559.678us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 4.000s 1747.206us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 269.736us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 13.567us 1 1 100.00
dma_csr_aliasing 4.000s 1747.206us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 36.000s 10201.243us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 395.000s 136062.891us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 883.000s 73024.390us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 883.000s 73024.390us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 395.000s 136062.891us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 644.000s 252795.720us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 883.000s 73024.390us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 14.000s 2814.099us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 185.000s 26768.608us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 13.754us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 25.599us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 4.000s 174.360us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 4.000s 174.360us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 53.203us 1 1 100.00
dma_csr_rw 2.000s 13.567us 1 1 100.00
dma_csr_aliasing 4.000s 1747.206us 1 1 100.00
dma_same_csr_outstanding 2.000s 73.394us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 53.203us 1 1 100.00
dma_csr_rw 2.000s 13.567us 1 1 100.00
dma_csr_aliasing 4.000s 1747.206us 1 1 100.00
dma_same_csr_outstanding 2.000s 73.394us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 10.000s 205.355us 1 1 100.00
dma_generic_stress 644.000s 252795.720us 1 1 100.00
dma_handshake_stress 883.000s 73024.390us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 9.000s 1988.905us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 146.093us 1 1 100.00
dma_sec_cm 1.000s 92.410us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 119.000s 51584.198us 1 1 100.00
dma_longer_transfer 3.000s 104.442us 1 1 100.00
dma_stress_all_with_rand_reset 2.000s 1302.783us 0 1 0.00