Simulation Results: edn

 
25/11/2025 16:03:05 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 83.79
  • line
  • 97.91
  • cond
  • 87.86
  • toggle
  • 83.97
  • fsm
  • 51.74
  • branch
  • 92.96
  • assert
  • 95.56
  • group
  • 76.53
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.330s 29.033us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.900s 42.277us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.780s 22.715us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.420s 263.959us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.150s 44.357us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.520s 54.621us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.780s 22.715us 1 1 100.00
edn_csr_aliasing 1.150s 44.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.300s 55.829us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.300s 55.829us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.300s 55.829us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.860s 63.619us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.110s 129.445us 1 1 100.00
errs 1 1 100.00
edn_err 0.990s 23.106us 1 1 100.00
disable 2 2 100.00
edn_disable 0.770s 19.867us 1 1 100.00
edn_disable_auto_req_mode 1.210s 81.655us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.670s 307.693us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.850s 42.590us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.010s 17.501us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.390s 35.647us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.390s 35.647us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.900s 42.277us 1 1 100.00
edn_csr_rw 0.780s 22.715us 1 1 100.00
edn_csr_aliasing 1.150s 44.357us 1 1 100.00
edn_same_csr_outstanding 1.090s 33.656us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.900s 42.277us 1 1 100.00
edn_csr_rw 0.780s 22.715us 1 1 100.00
edn_csr_aliasing 1.150s 44.357us 1 1 100.00
edn_same_csr_outstanding 1.090s 33.656us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.920s 264.196us 1 1 100.00
edn_tl_intg_err 1.430s 137.891us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.870s 32.446us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.110s 129.445us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.920s 264.196us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.920s 264.196us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.920s 264.196us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.920s 264.196us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.110s 129.445us 1 1 100.00
edn_sec_cm 3.920s 264.196us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.110s 129.445us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.430s 137.891us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 51.990s 5251.355us 1 1 100.00