Simulation Results: hmac

 
25/11/2025 16:03:05 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 90.2
  • line
  • 99.79
  • cond
  • 96.68
  • toggle
  • 100.0
  • fsm
  • 94.12
  • branch
  • 99.67
  • assert
  • 97.14
  • group
  • 44.02
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.050s 50.476us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.030s 58.839us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.680s 48.250us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.040s 115.088us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.910s 107.023us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.140s 66.561us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.680s 48.250us 1 1 100.00
hmac_csr_aliasing 3.910s 107.023us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 41.650s 5665.311us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 62.250s 2621.437us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.120s 716.741us 1 1 100.00
hmac_test_sha384_vectors 19.500s 798.620us 1 1 100.00
hmac_test_sha512_vectors 348.510s 10471.788us 1 1 100.00
hmac_test_hmac256_vectors 10.220s 645.939us 1 1 100.00
hmac_test_hmac384_vectors 9.960s 349.386us 1 1 100.00
hmac_test_hmac512_vectors 8.730s 532.514us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 9.520s 4087.538us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 1185.540s 14594.362us 1 1 100.00
error 1 1 100.00
hmac_error 73.500s 3536.677us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 26.430s 5690.300us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.050s 50.476us 1 1 100.00
hmac_long_msg 41.650s 5665.311us 1 1 100.00
hmac_back_pressure 62.250s 2621.437us 1 1 100.00
hmac_datapath_stress 1185.540s 14594.362us 1 1 100.00
hmac_burst_wr 9.520s 4087.538us 1 1 100.00
hmac_stress_all 21.910s 2076.820us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.050s 50.476us 1 1 100.00
hmac_long_msg 41.650s 5665.311us 1 1 100.00
hmac_back_pressure 62.250s 2621.437us 1 1 100.00
hmac_datapath_stress 1185.540s 14594.362us 1 1 100.00
hmac_wipe_secret 26.430s 5690.300us 1 1 100.00
hmac_test_sha256_vectors 8.120s 716.741us 1 1 100.00
hmac_test_sha384_vectors 19.500s 798.620us 1 1 100.00
hmac_test_sha512_vectors 348.510s 10471.788us 1 1 100.00
hmac_test_hmac256_vectors 10.220s 645.939us 1 1 100.00
hmac_test_hmac384_vectors 9.960s 349.386us 1 1 100.00
hmac_test_hmac512_vectors 8.730s 532.514us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.050s 50.476us 1 1 100.00
hmac_long_msg 41.650s 5665.311us 1 1 100.00
hmac_back_pressure 62.250s 2621.437us 1 1 100.00
hmac_datapath_stress 1185.540s 14594.362us 1 1 100.00
hmac_burst_wr 9.520s 4087.538us 1 1 100.00
hmac_error 73.500s 3536.677us 1 1 100.00
hmac_wipe_secret 26.430s 5690.300us 1 1 100.00
hmac_test_sha256_vectors 8.120s 716.741us 1 1 100.00
hmac_test_sha384_vectors 19.500s 798.620us 1 1 100.00
hmac_test_sha512_vectors 348.510s 10471.788us 1 1 100.00
hmac_test_hmac256_vectors 10.220s 645.939us 1 1 100.00
hmac_test_hmac384_vectors 9.960s 349.386us 1 1 100.00
hmac_test_hmac512_vectors 8.730s 532.514us 1 1 100.00
hmac_stress_all 21.910s 2076.820us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 21.910s 2076.820us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.640s 11.686us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.760s 17.659us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.280s 1167.763us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.280s 1167.763us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.030s 58.839us 1 1 100.00
hmac_csr_rw 0.680s 48.250us 1 1 100.00
hmac_csr_aliasing 3.910s 107.023us 1 1 100.00
hmac_same_csr_outstanding 2.010s 336.100us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.030s 58.839us 1 1 100.00
hmac_csr_rw 0.680s 48.250us 1 1 100.00
hmac_csr_aliasing 3.910s 107.023us 1 1 100.00
hmac_same_csr_outstanding 2.010s 336.100us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 2.380s 309.676us 1 1 100.00
hmac_sec_cm 1.150s 346.068us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.380s 309.676us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.050s 50.476us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.080s 63.959us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 125.610s 2480.228us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.590s 394.477us 1 1 100.00