| host_error_intr |
0 |
1 |
0.00 |
|
i2c_host_error_intr |
0.980s |
13.294us |
0 |
1 |
0.00
|
| host_stress_all |
0 |
1 |
0.00 |
|
i2c_host_stress_all |
886.460s |
86257.171us |
0 |
1 |
0.00
|
| host_maxperf |
1 |
1 |
100.00 |
|
i2c_host_perf |
20.270s |
2760.780us |
1 |
1 |
100.00
|
| host_override |
1 |
1 |
100.00 |
|
i2c_host_override |
0.910s |
49.383us |
1 |
1 |
100.00
|
| host_fifo_watermark |
1 |
1 |
100.00 |
|
i2c_host_fifo_watermark |
38.600s |
7134.549us |
1 |
1 |
100.00
|
| host_fifo_overflow |
1 |
1 |
100.00 |
|
i2c_host_fifo_overflow |
24.380s |
1290.598us |
1 |
1 |
100.00
|
| host_fifo_reset |
3 |
3 |
100.00 |
|
i2c_host_fifo_reset_fmt |
1.290s |
129.915us |
1 |
1 |
100.00
|
|
i2c_host_fifo_fmt_empty |
22.610s |
2373.311us |
1 |
1 |
100.00
|
|
i2c_host_fifo_reset_rx |
3.340s |
129.798us |
1 |
1 |
100.00
|
| host_fifo_full |
1 |
1 |
100.00 |
|
i2c_host_fifo_full |
63.590s |
13874.644us |
1 |
1 |
100.00
|
| host_timeout |
1 |
1 |
100.00 |
|
i2c_host_stretch_timeout |
24.410s |
1516.133us |
1 |
1 |
100.00
|
| i2c_host_mode_toggle |
1 |
1 |
100.00 |
|
i2c_host_mode_toggle |
1.290s |
247.606us |
1 |
1 |
100.00
|
| target_glitch |
0 |
1 |
0.00 |
|
i2c_target_glitch |
2.590s |
1686.346us |
0 |
1 |
0.00
|
| target_stress_all |
1 |
1 |
100.00 |
|
i2c_target_stress_all |
21.630s |
18642.137us |
1 |
1 |
100.00
|
| target_maxperf |
1 |
1 |
100.00 |
|
i2c_target_perf |
2.790s |
852.772us |
1 |
1 |
100.00
|
| target_fifo_empty |
2 |
2 |
100.00 |
|
i2c_target_stress_rd |
27.070s |
2073.135us |
1 |
1 |
100.00
|
|
i2c_target_intr_smoke |
3.920s |
3288.232us |
1 |
1 |
100.00
|
| target_fifo_reset |
2 |
2 |
100.00 |
|
i2c_target_fifo_reset_acq |
0.940s |
242.087us |
1 |
1 |
100.00
|
|
i2c_target_fifo_reset_tx |
1.170s |
193.439us |
1 |
1 |
100.00
|
| target_fifo_full |
3 |
3 |
100.00 |
|
i2c_target_stress_wr |
6.560s |
8425.890us |
1 |
1 |
100.00
|
|
i2c_target_stress_rd |
27.070s |
2073.135us |
1 |
1 |
100.00
|
|
i2c_target_intr_stress_wr |
3.320s |
5329.793us |
1 |
1 |
100.00
|
| target_timeout |
1 |
1 |
100.00 |
|
i2c_target_timeout |
4.890s |
5401.584us |
1 |
1 |
100.00
|
| target_clock_stretch |
0 |
1 |
0.00 |
|
i2c_target_stretch |
17.040s |
10012.017us |
0 |
1 |
0.00
|
| bad_address |
1 |
1 |
100.00 |
|
i2c_target_bad_addr |
3.930s |
4143.424us |
1 |
1 |
100.00
|
| target_mode_glitch |
0 |
1 |
0.00 |
|
i2c_target_hrst |
5.380s |
10056.573us |
0 |
1 |
0.00
|
| target_fifo_watermark |
2 |
2 |
100.00 |
|
i2c_target_fifo_watermarks_acq |
2.750s |
1314.637us |
1 |
1 |
100.00
|
|
i2c_target_fifo_watermarks_tx |
0.950s |
174.946us |
1 |
1 |
100.00
|
| host_mode_config_perf |
2 |
2 |
100.00 |
|
i2c_host_perf |
20.270s |
2760.780us |
1 |
1 |
100.00
|
|
i2c_host_perf_precise |
1.860s |
72.470us |
1 |
1 |
100.00
|
| host_mode_clock_stretching |
1 |
1 |
100.00 |
|
i2c_host_stretch_timeout |
24.410s |
1516.133us |
1 |
1 |
100.00
|
| target_mode_tx_stretch_ctrl |
1 |
1 |
100.00 |
|
i2c_target_tx_stretch_ctrl |
2.720s |
189.860us |
1 |
1 |
100.00
|
| target_mode_nack_generation |
2 |
3 |
66.67 |
|
i2c_target_nack_acqfull |
2.270s |
1023.772us |
1 |
1 |
100.00
|
|
i2c_target_nack_acqfull_addr |
2.200s |
618.723us |
1 |
1 |
100.00
|
|
i2c_target_nack_txstretch |
1.980s |
138.421us |
0 |
1 |
0.00
|
| host_mode_halt_on_nak |
1 |
1 |
100.00 |
|
i2c_host_may_nack |
3.570s |
1170.290us |
1 |
1 |
100.00
|
| target_mode_smbus_maxlen |
1 |
1 |
100.00 |
|
i2c_target_smbus_maxlen |
1.850s |
2962.584us |
1 |
1 |
100.00
|
| alert_test |
1 |
1 |
100.00 |
|
i2c_alert_test |
0.920s |
26.410us |
1 |
1 |
100.00
|
| intr_test |
1 |
1 |
100.00 |
|
i2c_intr_test |
0.820s |
19.417us |
1 |
1 |
100.00
|
| tl_d_oob_addr_access |
1 |
1 |
100.00 |
|
i2c_tl_errors |
1.720s |
900.682us |
1 |
1 |
100.00
|
| tl_d_illegal_access |
1 |
1 |
100.00 |
|
i2c_tl_errors |
1.720s |
900.682us |
1 |
1 |
100.00
|
| tl_d_outstanding_access |
4 |
4 |
100.00 |
|
i2c_csr_hw_reset |
0.830s |
30.949us |
1 |
1 |
100.00
|
|
i2c_csr_rw |
0.840s |
38.989us |
1 |
1 |
100.00
|
|
i2c_csr_aliasing |
1.630s |
112.704us |
1 |
1 |
100.00
|
|
i2c_same_csr_outstanding |
1.410s |
62.284us |
1 |
1 |
100.00
|
| tl_d_partial_access |
4 |
4 |
100.00 |
|
i2c_csr_hw_reset |
0.830s |
30.949us |
1 |
1 |
100.00
|
|
i2c_csr_rw |
0.840s |
38.989us |
1 |
1 |
100.00
|
|
i2c_csr_aliasing |
1.630s |
112.704us |
1 |
1 |
100.00
|
|
i2c_same_csr_outstanding |
1.410s |
62.284us |
1 |
1 |
100.00
|