Simulation Results: lc_ctrl

 
25/11/2025 16:03:05 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 89.1
  • line
  • 97.64
  • cond
  • 79.84
  • toggle
  • 82.82
  • fsm
  • 80.95
  • branch
  • 96.34
  • assert
  • 95.99
  • group
  • 90.11
Validation stages
V1
100.00%
V2
90.00%
V2S
71.43%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.270s 106.456us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.810s 38.727us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.010s 114.073us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.220s 19.621us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.020s 129.869us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.320s 80.667us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.010s 114.073us 1 1 100.00
lc_ctrl_csr_aliasing 1.020s 129.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 6.550s 139.966us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.370s 1033.630us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.110s 13.946us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.970s 379.523us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 1.260s 8.092us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.940s 3213.898us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 1.260s 8.092us 0 1 0.00
lc_ctrl_prog_failure 1.970s 379.523us 1 1 100.00
lc_ctrl_errors 4.940s 3213.898us 1 1 100.00
lc_ctrl_security_escalation 5.020s 5586.626us 1 1 100.00
lc_ctrl_jtag_state_failure 1.980s 249.922us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.180s 197.138us 1 1 100.00
lc_ctrl_jtag_errors 46.600s 4870.363us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 8.030s 4179.197us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.130s 329.248us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.180s 197.138us 1 1 100.00
lc_ctrl_jtag_errors 46.600s 4870.363us 1 1 100.00
lc_ctrl_jtag_access 5.930s 696.400us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 16.610s 861.537us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 124.338us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.540s 85.696us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.920s 3343.696us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.800s 562.988us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.130s 45.017us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.740s 103.492us 1 1 100.00
lc_ctrl_jtag_alert_test 0.860s 24.250us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.030s 721.975us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.040s 43.769us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 9.140s 504.954us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.180s 30.358us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.730s 190.919us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.730s 190.919us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.810s 38.727us 1 1 100.00
lc_ctrl_csr_rw 1.010s 114.073us 1 1 100.00
lc_ctrl_csr_aliasing 1.020s 129.869us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.200s 85.481us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.810s 38.727us 1 1 100.00
lc_ctrl_csr_rw 1.010s 114.073us 1 1 100.00
lc_ctrl_csr_aliasing 1.020s 129.869us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.200s 85.481us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.480s 131.939us 1 1 100.00
lc_ctrl_tl_intg_err 1.940s 256.850us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.940s 256.850us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.370s 1033.630us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 1.260s 8.092us 0 1 0.00
lc_ctrl_sec_cm 6.480s 131.939us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 1.260s 8.092us 0 1 0.00
lc_ctrl_sec_cm 6.480s 131.939us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.260s 8.092us 0 1 0.00
lc_ctrl_sec_cm 6.480s 131.939us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.260s 8.092us 0 1 0.00
lc_ctrl_sec_cm 6.480s 131.939us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 1.260s 8.092us 0 1 0.00
lc_ctrl_sec_cm 6.480s 131.939us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.260s 8.092us 0 1 0.00
lc_ctrl_sec_cm 6.480s 131.939us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.260s 8.092us 0 1 0.00
lc_ctrl_sec_cm 6.480s 131.939us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 1.260s 8.092us 0 1 0.00
lc_ctrl_sec_cm 6.480s 131.939us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.020s 5586.626us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 6.550s 139.966us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.130s 329.248us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.280s 267.589us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.280s 267.589us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.170s 1130.556us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.090s 439.862us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.090s 439.862us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 21.770s 6954.449us 1 1 100.00