Simulation Results: lc_ctrl

 
25/11/2025 16:03:05 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 87.14
  • line
  • 97.5
  • cond
  • 78.67
  • toggle
  • 75.39
  • fsm
  • 81.4
  • branch
  • 95.59
  • assert
  • 95.99
  • group
  • 85.43
Validation stages
V1
100.00%
V2
87.50%
V2S
64.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.250s 31.959us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.900s 33.558us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.930s 63.365us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.910s 20.490us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.940s 36.272us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.950s 17.977us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.930s 63.365us 1 1 100.00
lc_ctrl_csr_aliasing 0.940s 36.272us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 1.540s 52.760us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.520s 971.619us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.890s 20.458us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.980s 50.891us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 6.040s 1258.884us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.050s 220.014us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 6.040s 1258.884us 0 1 0.00
lc_ctrl_prog_failure 1.980s 50.891us 1 1 100.00
lc_ctrl_errors 4.050s 220.014us 1 1 100.00
lc_ctrl_security_escalation 5.350s 855.655us 1 1 100.00
lc_ctrl_jtag_state_failure 2.540s 84.175us 0 1 0.00
lc_ctrl_jtag_prog_failure 7.050s 689.465us 1 1 100.00
lc_ctrl_jtag_errors 18.000s 9103.683us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_csr_hw_reset 1.670s 431.903us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.310s 310.682us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.760s 1205.748us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.790s 1732.780us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.490s 39.987us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.830s 395.876us 1 1 100.00
lc_ctrl_jtag_alert_test 1.270s 36.096us 1 1 100.00
lc_ctrl_jtag_smoke 4.420s 596.200us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.100s 1074.887us 0 1 0.00
lc_ctrl_jtag_prog_failure 7.050s 689.465us 1 1 100.00
lc_ctrl_jtag_errors 18.000s 9103.683us 1 1 100.00
lc_ctrl_jtag_access 4.940s 505.843us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.090s 1847.033us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.390s 4739.901us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.990s 16.275us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 29.390s 12212.090us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.010s 75.648us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.860s 55.390us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.860s 55.390us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.900s 33.558us 1 1 100.00
lc_ctrl_csr_rw 0.930s 63.365us 1 1 100.00
lc_ctrl_csr_aliasing 0.940s 36.272us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.070s 24.684us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.900s 33.558us 1 1 100.00
lc_ctrl_csr_rw 0.930s 63.365us 1 1 100.00
lc_ctrl_csr_aliasing 0.940s 36.272us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.070s 24.684us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.570s 231.386us 1 1 100.00
lc_ctrl_sec_cm 6.290s 128.801us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.570s 231.386us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.520s 971.619us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 6.040s 1258.884us 0 1 0.00
lc_ctrl_sec_cm 6.290s 128.801us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 6.040s 1258.884us 0 1 0.00
lc_ctrl_sec_cm 6.290s 128.801us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 6.040s 1258.884us 0 1 0.00
lc_ctrl_sec_cm 6.290s 128.801us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 6.040s 1258.884us 0 1 0.00
lc_ctrl_sec_cm 6.290s 128.801us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 6.040s 1258.884us 0 1 0.00
lc_ctrl_sec_cm 6.290s 128.801us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 6.040s 1258.884us 0 1 0.00
lc_ctrl_sec_cm 6.290s 128.801us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 6.040s 1258.884us 0 1 0.00
lc_ctrl_sec_cm 6.290s 128.801us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 6.040s 1258.884us 0 1 0.00
lc_ctrl_sec_cm 6.290s 128.801us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.350s 855.655us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 1.540s 52.760us 0 1 0.00
lc_ctrl_jtag_state_post_trans 13.100s 1074.887us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.680s 321.898us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.680s 321.898us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.920s 339.431us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.420s 1386.448us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.420s 1386.448us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 44.160s 4397.396us 0 1 0.00