Simulation Results: rom_ctrl

 
25/11/2025 16:03:05 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 97.57
  • line
  • 99.32
  • cond
  • 98.07
  • toggle
  • 99.92
  • fsm
  • 93.33
  • branch
  • 98.91
  • assert
  • 96.8
  • group
  • 96.66
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.150s 141.743us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.370s 954.157us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.940s 402.620us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.470s 129.686us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.550s 134.993us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.420s 135.068us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.940s 402.620us 1 1 100.00
rom_ctrl_csr_aliasing 3.550s 134.993us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.930s 385.499us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.960s 206.560us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 3.620s 426.905us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 8.670s 1880.496us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.570s 1693.382us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.300s 137.431us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.780s 406.888us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.780s 406.888us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.370s 954.157us 1 1 100.00
rom_ctrl_csr_rw 2.940s 402.620us 1 1 100.00
rom_ctrl_csr_aliasing 3.550s 134.993us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.530s 132.359us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.370s 954.157us 1 1 100.00
rom_ctrl_csr_rw 2.940s 402.620us 1 1 100.00
rom_ctrl_csr_aliasing 3.550s 134.993us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.530s 132.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.200s 10885.124us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.930s 592.675us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 196.380s 588.585us 1 1 100.00
rom_ctrl_tl_intg_err 22.230s 1535.763us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 196.380s 588.585us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 196.380s 588.585us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.200s 10885.124us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.200s 10885.124us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.200s 10885.124us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.200s 10885.124us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.200s 10885.124us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 196.380s 588.585us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 196.380s 588.585us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.150s 141.743us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.150s 141.743us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.150s 141.743us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 22.230s 1535.763us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.200s 10885.124us 1 1 100.00
rom_ctrl_kmac_err_chk 6.570s 1693.382us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.200s 10885.124us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.200s 10885.124us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.200s 10885.124us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.930s 592.675us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 196.380s 588.585us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 191.130s 17825.355us 1 1 100.00