Simulation Results: rom_ctrl

 
25/11/2025 16:03:05 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 98.56
  • line
  • 99.46
  • cond
  • 97.62
  • toggle
  • 100.0
  • fsm
  • 100.0
  • branch
  • 98.91
  • assert
  • 96.8
  • group
  • 97.14
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.650s 1103.800us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.600s 842.627us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.490s 728.441us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.690s 547.598us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.520s 955.735us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.190s 299.527us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.490s 728.441us 1 1 100.00
rom_ctrl_csr_aliasing 5.520s 955.735us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.840s 579.763us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.410s 577.580us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 8.170s 312.361us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 21.080s 1909.815us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.590s 1121.671us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.050s 291.838us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.000s 1008.040us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.000s 1008.040us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.600s 842.627us 1 1 100.00
rom_ctrl_csr_rw 5.490s 728.441us 1 1 100.00
rom_ctrl_csr_aliasing 5.520s 955.735us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.030s 222.007us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.600s 842.627us 1 1 100.00
rom_ctrl_csr_rw 5.490s 728.441us 1 1 100.00
rom_ctrl_csr_aliasing 5.520s 955.735us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.030s 222.007us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 123.010s 14151.054us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 26.980s 1067.117us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 234.260s 553.941us 1 1 100.00
rom_ctrl_tl_intg_err 95.680s 669.668us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 234.260s 553.941us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 234.260s 553.941us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 123.010s 14151.054us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 123.010s 14151.054us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 123.010s 14151.054us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 123.010s 14151.054us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 123.010s 14151.054us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 234.260s 553.941us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 234.260s 553.941us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.650s 1103.800us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.650s 1103.800us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.650s 1103.800us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 95.680s 669.668us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 123.010s 14151.054us 1 1 100.00
rom_ctrl_kmac_err_chk 13.590s 1121.671us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 123.010s 14151.054us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 123.010s 14151.054us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 123.010s 14151.054us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 26.980s 1067.117us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 234.260s 553.941us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 117.190s 11114.133us 1 1 100.00