Simulation Results: rstmgr

 
25/11/2025 16:03:05 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 98.73
  • line
  • 99.19
  • cond
  • 98.52
  • toggle
  • 99.62
  • fsm
  • None
  • branch
  • 99.72
  • assert
  • 97.44
  • group
  • 97.89
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.230s 71.381us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.430s 65.069us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.030s 36.890us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.600s 116.957us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.750s 50.221us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.310s 93.779us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.030s 36.890us 1 1 100.00
rstmgr_csr_aliasing 1.750s 50.221us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.740s 196.453us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.990s 43.381us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.940s 43.618us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.890s 685.618us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.890s 685.618us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.890s 685.618us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.890s 685.618us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 31.160s 4445.101us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.920s 43.122us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 3.430s 82.894us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 3.430s 82.894us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.430s 65.069us 1 1 100.00
rstmgr_csr_rw 1.030s 36.890us 1 1 100.00
rstmgr_csr_aliasing 1.750s 50.221us 1 1 100.00
rstmgr_same_csr_outstanding 1.600s 71.291us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.430s 65.069us 1 1 100.00
rstmgr_csr_rw 1.030s 36.890us 1 1 100.00
rstmgr_csr_aliasing 1.750s 50.221us 1 1 100.00
rstmgr_same_csr_outstanding 1.600s 71.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_tl_intg_err 6.690s 619.307us 1 1 100.00
rstmgr_sec_cm 16.630s 3407.383us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 16.630s 3407.383us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 16.630s 3407.383us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 6.690s 619.307us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.140s 62.905us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.430s 420.599us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.170s 291.598us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 16.630s 3407.383us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.030s 36.890us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.030s 36.890us 1 1 100.00