| V1 |
|
90.32% |
| V2 |
|
60.71% |
| V2S |
|
75.00% |
| V3 |
|
0.00% |
| unmapped |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| rv_dm_smoke | 10.370s | 11655.663us | 0 | 1 | 0.00 | |
| jtag_dtm_csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_hw_reset | 1.710s | 1091.756us | 1 | 1 | 100.00 | |
| jtag_dtm_csr_rw | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_rw | 1.270s | 370.618us | 1 | 1 | 100.00 | |
| jtag_dtm_csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_bit_bash | 2.020s | 6769.945us | 1 | 1 | 100.00 | |
| jtag_dtm_csr_aliasing | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_aliasing | 0.870s | 445.259us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_hw_reset | 13.700s | 7081.291us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_rw | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_rw | 4.570s | 7614.714us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_bit_bash | 2.950s | 3983.857us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_aliasing | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_aliasing | 59.950s | 127898.187us | 1 | 1 | 100.00 | |
| jtag_dmi_cmderr_busy | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_busy | 1.070s | 1427.948us | 1 | 1 | 100.00 | |
| jtag_dmi_cmderr_not_supported | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_not_supported | 1.220s | 514.872us | 1 | 1 | 100.00 | |
| cmderr_exception | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_exception | 1.000s | 196.985us | 1 | 1 | 100.00 | |
| mem_tl_access_resuming | 0 | 1 | 0.00 | |||
| rv_dm_mem_tl_access_resuming | 0.810s | 94.644us | 0 | 1 | 0.00 | |
| mem_tl_access_halted | 1 | 1 | 100.00 | |||
| rv_dm_mem_tl_access_halted | 0.700s | 188.950us | 1 | 1 | 100.00 | |
| cmderr_halt_resume | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_halt_resume | 1.280s | 1357.011us | 1 | 1 | 100.00 | |
| dataaddr_rw_access | 1 | 1 | 100.00 | |||
| rv_dm_dataaddr_rw_access | 0.640s | 86.347us | 1 | 1 | 100.00 | |
| halt_resume | 1 | 1 | 100.00 | |||
| rv_dm_halt_resume_whereto | 1.850s | 1329.349us | 1 | 1 | 100.00 | |
| progbuf_busy | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_busy | 1.070s | 1427.948us | 1 | 1 | 100.00 | |
| abstractcmd_status | 1 | 1 | 100.00 | |||
| rv_dm_abstractcmd_status | 0.730s | 174.164us | 1 | 1 | 100.00 | |
| progbuf_read_write_execute | 1 | 1 | 100.00 | |||
| rv_dm_progbuf_read_write_execute | 1.060s | 998.176us | 1 | 1 | 100.00 | |
| progbuf_exception | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_exception | 1.000s | 196.985us | 1 | 1 | 100.00 | |
| rom_read_access | 1 | 1 | 100.00 | |||
| rv_dm_rom_read_access | 0.780s | 44.285us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_dm_csr_hw_reset | 1.140s | 131.431us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rv_dm_csr_rw | 1.580s | 351.107us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_dm_csr_bit_bash | 24.500s | 15874.863us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_dm_csr_aliasing | 19.510s | 4586.010us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_dm_csr_mem_rw_with_rand_reset | 0.680s | 51.914us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rv_dm_csr_aliasing | 19.510s | 4586.010us | 1 | 1 | 100.00 | |
| rv_dm_csr_rw | 1.580s | 351.107us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| rv_dm_mem_walk | 0.690s | 168.648us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| rv_dm_mem_partial_access | 0.680s | 55.108us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| idcode | 0 | 1 | 0.00 | |||
| rv_dm_smoke | 10.370s | 11655.663us | 0 | 1 | 0.00 | |
| jtag_dtm_hard_reset | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_hard_reset | 0.800s | 197.579us | 1 | 1 | 100.00 | |
| jtag_dtm_idle_hint | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_idle_hint | 0.860s | 171.377us | 1 | 1 | 100.00 | |
| jtag_dmi_failed_op | 1 | 1 | 100.00 | |||
| rv_dm_dmi_failed_op | 0.870s | 190.321us | 1 | 1 | 100.00 | |
| jtag_dmi_dm_inactive | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_dm_inactive | 3.340s | 1582.483us | 1 | 1 | 100.00 | |
| sba | 0 | 2 | 0.00 | |||
| rv_dm_sba_tl_access | 515.910s | 300000.000us | 0 | 1 | 0.00 | |
| rv_dm_delayed_resp_sba_tl_access | 99.490s | 300000.000us | 0 | 1 | 0.00 | |
| bad_sba | 0 | 1 | 0.00 | |||
| rv_dm_bad_sba_tl_access | 327.230s | 300000.000us | 0 | 1 | 0.00 | |
| sba_autoincrement | 0 | 1 | 0.00 | |||
| rv_dm_autoincr_sba_tl_access | 271.380s | 300000.000us | 0 | 1 | 0.00 | |
| jtag_dmi_debug_disabled | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dmi_debug_disabled | 0.910s | 140.823us | 0 | 1 | 0.00 | |
| sba_debug_disabled | 1 | 1 | 100.00 | |||
| rv_dm_sba_debug_disabled | 0.750s | 664.750us | 1 | 1 | 100.00 | |
| ndmreset_req | 1 | 1 | 100.00 | |||
| rv_dm_ndmreset_req | 1.500s | 773.407us | 1 | 1 | 100.00 | |
| hart_unavail | 0 | 1 | 0.00 | |||
| rv_dm_hart_unavail | 0.740s | 118.935us | 0 | 1 | 0.00 | |
| tap_ctrl_transitions | 1 | 2 | 50.00 | |||
| rv_dm_tap_fsm_rand_reset | 0.630s | 138.133us | 0 | 1 | 0.00 | |
| rv_dm_tap_fsm | 5.080s | 8454.499us | 1 | 1 | 100.00 | |
| hartsel_warl | 1 | 1 | 100.00 | |||
| rv_dm_hartsel_warl | 0.850s | 436.719us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| rv_dm_stress_all | 2.120s | 2790.541us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rv_dm_alert_test | 0.720s | 144.518us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| rv_dm_tl_errors | 0.690s | 31.571us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| rv_dm_tl_errors | 0.690s | 31.571us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| rv_dm_csr_aliasing | 19.510s | 4586.010us | 1 | 1 | 100.00 | |
| rv_dm_csr_hw_reset | 1.140s | 131.431us | 1 | 1 | 100.00 | |
| rv_dm_csr_rw | 1.580s | 351.107us | 1 | 1 | 100.00 | |
| rv_dm_same_csr_outstanding | 2.770s | 255.102us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| rv_dm_csr_aliasing | 19.510s | 4586.010us | 1 | 1 | 100.00 | |
| rv_dm_csr_hw_reset | 1.140s | 131.431us | 1 | 1 | 100.00 | |
| rv_dm_csr_rw | 1.580s | 351.107us | 1 | 1 | 100.00 | |
| rv_dm_same_csr_outstanding | 2.770s | 255.102us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| rv_dm_tl_intg_err | 14.120s | 4628.746us | 1 | 1 | 100.00 | |
| rv_dm_sec_cm | 1.960s | 1262.387us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rv_dm_tl_intg_err | 14.120s | 4628.746us | 1 | 1 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 1 | 2 | 50.00 | |||
| rv_dm_sba_debug_disabled | 0.750s | 664.750us | 1 | 1 | 100.00 | |
| rv_dm_debug_disabled | 0.970s | 134.066us | 0 | 1 | 0.00 | |
| sec_cm_lc_dft_en_intersig_mubi | 1 | 2 | 50.00 | |||
| rv_dm_sba_debug_disabled | 0.750s | 664.750us | 1 | 1 | 100.00 | |
| rv_dm_debug_disabled | 0.970s | 134.066us | 0 | 1 | 0.00 | |
| sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 1 | 0.00 | |||
| rv_dm_smoke | 10.370s | 11655.663us | 0 | 1 | 0.00 | |
| sec_cm_dm_en_ctrl_lc_gated | 1 | 1 | 100.00 | |||
| rv_dm_buffered_enable | 1.000s | 195.161us | 1 | 1 | 100.00 | |
| sec_cm_sba_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| rv_dm_sparse_lc_gate_fsm | 0.860s | 172.799us | 1 | 1 | 100.00 | |
| sec_cm_mem_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| rv_dm_sparse_lc_gate_fsm | 0.860s | 172.799us | 1 | 1 | 100.00 | |
| sec_cm_exec_ctrl_mubi | 1 | 1 | 100.00 | |||
| rv_dm_buffered_enable | 1.000s | 195.161us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_dm_stress_all_with_rand_reset | 0.690s | 24.191us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 0 | 1 | 0.00 | |||
| rv_dm_scanmode | 581.060s | 300000.000us | 0 | 1 | 0.00 | |