Simulation Results: spi_device

 
25/11/2025 16:03:05 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 90.76
  • line
  • 99.08
  • cond
  • 96.16
  • toggle
  • 83.54
  • fsm
  • 89.36
  • branch
  • 98.33
  • assert
  • 94.3
  • group
  • 74.55
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 26.580s 11726.376us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.220s 20.648us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.220s 48.461us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 9.570s 1851.043us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.210s 1150.447us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.530s 99.330us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.220s 48.461us 1 1 100.00
spi_device_csr_aliasing 5.210s 1150.447us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.760s 52.989us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.750s 27.372us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.830s 104.823us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.820s 1.518us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.810s 4.747us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 3.700s 205.960us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 3.700s 205.960us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 10.120s 23609.095us 1 1 100.00
spi_device_tpm_sts_read 0.900s 35.456us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 11.410s 8430.530us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 6.100s 738.168us 1 1 100.00
spi_device_flash_all 348.720s 154070.872us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.060s 225.327us 1 1 100.00
spi_device_flash_all 348.720s 154070.872us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.060s 225.327us 1 1 100.00
spi_device_flash_all 348.720s 154070.872us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 348.720s 154070.872us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 6.050s 663.343us 1 1 100.00
spi_device_flash_all 348.720s 154070.872us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 6.050s 663.343us 1 1 100.00
spi_device_flash_all 348.720s 154070.872us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 6.050s 663.343us 1 1 100.00
spi_device_flash_all 348.720s 154070.872us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 6.050s 663.343us 1 1 100.00
spi_device_flash_all 348.720s 154070.872us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 6.050s 663.343us 1 1 100.00
spi_device_flash_all 348.720s 154070.872us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 20.480s 18007.185us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 2.540s 293.340us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 2.540s 293.340us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 2.540s 293.340us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 23.970s 9720.379us 1 1 100.00
spi_device_read_buffer_direct 3.840s 1855.675us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 2.540s 293.340us 1 1 100.00
spi_device_flash_all 348.720s 154070.872us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 348.720s 154070.872us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 348.720s 154070.872us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 1.810s 82.712us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 1.810s 82.712us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 26.580s 11726.376us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 65.280s 48950.373us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 68.930s 44862.983us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.760s 43.744us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.910s 14.756us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.980s 604.364us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.980s 604.364us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.220s 20.648us 1 1 100.00
spi_device_csr_rw 1.220s 48.461us 1 1 100.00
spi_device_csr_aliasing 5.210s 1150.447us 1 1 100.00
spi_device_same_csr_outstanding 1.480s 223.972us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.220s 20.648us 1 1 100.00
spi_device_csr_rw 1.220s 48.461us 1 1 100.00
spi_device_csr_aliasing 5.210s 1150.447us 1 1 100.00
spi_device_same_csr_outstanding 1.480s 223.972us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.360s 625.630us 1 1 100.00
spi_device_tl_intg_err 9.040s 796.029us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 9.040s 796.029us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 59.100s 12860.317us 1 1 100.00