Simulation Results: sram_ctrl

 
25/11/2025 16:03:05 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 88.53
  • line
  • 96.69
  • cond
  • 91.43
  • toggle
  • 90.71
  • fsm
  • 57.14
  • branch
  • 94.31
  • assert
  • 95.55
  • group
  • 93.88
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 64.670s 943.769us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.940s 18.439us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.770s 15.001us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.870s 408.157us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.910s 18.705us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.440s 370.902us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.770s 15.001us 1 1 100.00
sram_ctrl_csr_aliasing 0.910s 18.705us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 120.400s 27805.882us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 58.360s 2685.489us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 460.600s 8791.621us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 222.920s 17267.352us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1595.160s 169380.317us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 432.660s 42448.331us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 41.600s 36768.710us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 101.180s 44570.180us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 13.710s 862.589us 1 1 100.00
sram_ctrl_partial_access_b2b 217.170s 22189.389us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 6.280s 1414.629us 1 1 100.00
sram_ctrl_throughput_w_partial_write 24.910s 14575.801us 1 1 100.00
sram_ctrl_throughput_w_readback 6.550s 730.622us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 506.770s 3571.634us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.370s 347.853us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 7993.680s 7986046.298us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.710s 36.516us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.880s 397.593us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.880s 397.593us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.940s 18.439us 1 1 100.00
sram_ctrl_csr_rw 0.770s 15.001us 1 1 100.00
sram_ctrl_csr_aliasing 0.910s 18.705us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.140s 43.350us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.940s 18.439us 1 1 100.00
sram_ctrl_csr_rw 0.770s 15.001us 1 1 100.00
sram_ctrl_csr_aliasing 0.910s 18.705us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.140s 43.350us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 29.450s 9686.974us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 1.540s 154.270us 1 1 100.00
sram_ctrl_sec_cm 0.970s 9.939us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.970s 9.939us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.540s 154.270us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 506.770s 3571.634us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 506.770s 3571.634us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.770s 15.001us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 101.180s 44570.180us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 101.180s 44570.180us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 101.180s 44570.180us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 41.600s 36768.710us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.860s 2787.073us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 29.450s 9686.974us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.020s 662.263us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 64.670s 943.769us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 64.670s 943.769us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 101.180s 44570.180us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.970s 9.939us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 41.600s 36768.710us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.970s 9.939us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.970s 9.939us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 64.670s 943.769us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.970s 9.939us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 7.650s 302.024us 1 1 100.00